How do I port EFM32 Series 0 (EFM32ZG, EFM32HG, EFM32TG, EFM32G, EFM32LG, EFM32GG, EFM32WG) MCU applications to EFM32 Series 1 (EFM32JG, EFM32PG)?
The EFM32 Series 1, such as Jade and Pearl Gecko, contain many enhancements to the core and peripherals.
For all common features and peripherals, the EFM32 Series 1 are software compatible with EFM32 Series 0 devices.
In order to take advantage of newly enhanced peripherals and features, users should update to the latest version of emlib and review the new software examples showing how to use these new features.
For more details, see AN0918 MCU Series 0 to EFM32JGxx/PGxx Compatibility and Migration Guide.. Application Notes can be found in Simplicity Studio > [Documentation] tab > [Application Notes] or here: www.silabs.com/32bit-appnotes.
How are the pin routes for the EFM32 Series 1, such as Jade and Pearl Gecko, different than EFM32 Series 0 devices?
EFM32 Series 0 Pin Routes
For EFM32 Series 0 devices, there is a single ROUTE register for each peripheral module that can be used to enable each pin for the peripheral independently. However there is only a single location bit field for the module. This means that there are less total pinout options.
For example, let's take a look at the EFM32WG ROUTE register for the USART modules:
Note that there are four pin enable bits for each of the pins within the module, but there is only a single location field for the entire module.
With the release of the next generation EFM32 Series 1, the pin routes for modules has been enhanced. Now, each module has a ROUTEPEN and one or more ROUTELOCn register. ROUTEPEN is used to enable or disable each pin for the module, and ROUTELOCn contains a separate bit field for each peripheral pin location.
For example, let's take a look at the EFM32JG ROUTEPEN and ROUTELOCn registers for the USART modules:
Note that pin enable bits have been moved to a new register, ROUTEPEN.
Note that there are multiple route location bit fields for each pin within the module.
Note that there may be more than one ROUTELOCn register for each module.
The end result is that each pin with its own dedicated route location field can use a location, independent of other pins in the module. This offers much greater flexibility in the number of possible pinout combinations.
For example, for EFM32JG, now the following pin route for USART0 is possible:
US0_CLK - Location 22 (PF0)
US0_CS - Location 5 (PB13)
US0_CTS - Location 12 (PC11)
US0_RTS - Location 9 (PC9)
US0_RX - Location 1 (PA1)
US0_TX - Location 31 (PF7)
What's new in the EFM32 Series 1 Clock Management Unit (CMU)?
There are several additions and improvements in the EFM32 Series 1 clock management unit (CMU).
EFM32 Series 1 have a new LFECLK branch used to power the new real-time clock with calendar (RTCC) module. The RTCC can operate down to EM4H. LFACLK and LFBCLK branches can now operate down to EM3.
The EFM32 HFCORECLK branch has now been split into HFCORECLK, HFEXPCLK, and HFBUSCLK branches.
The HFRCO now supports a wider oscillator frequency range, 1-38 MHz, up from 1-28 MHz. The new factory calibrated HFRCO bands are: 1, 2, 4, 7, 13, 16, 19, 26, 32, and 38 MHz. The default HFRCO band is 19 MHz instead of 14 MHz for EFM32 devices. The HFRCO 19 MHz band is used when waking up from lower power modes.
The HFXO only supports a limited 38-40 MHz oscillator frequency range.
Refer to AN0004 Clock Management Unit for more information and to view software examples that can be used to configure the CMU. Application Notes can be found in Simplicity Studio > [Documentation] tab > [Application Notes] or here: www.silabs.com/32bit-appnotes.
See the appropriate reference manual for complete details.
What's new in the EFM32 Series 1 CRYPTO Module?
The next generation EFM32 Series 1 products contain a hardware accelerated, fast, and energy efficient encryption and decryption engine.
The new CRYPTO module supports:
AES encryption and decryption with 128- or 256-bit keys, ECC over both GF(P) and GF(2m), and SHA-1 and SHA-2 (SHA-224 and SHA-256).
Supported modes of operation for AES include:
ECB, CTR, CBC, PCBC, CFB, OFB, CBC-MAC, GMAC and CCM.
Supported ECC NIST recommended curves include:
P-192, P-224, P-256, K-163, K-233, B-163 and B-233.
The CRYPTO module allows fast processing of GCM (AES), ECC, and SHA with little CPU intervention. CRYPTO also provides trigger signals for DMA read and write operations.
See AN0955 EFM32 CRYPTO and an EFM32 Series 1 Reference Manual for more details. Application Notes can be found in Simplicity Studio using the [Application Notes] tile or here: www.silabs.com/32bit-appnotes.
What's new in the EFM32 Series 1 (EFM32JG, EFM32PG) LDMA module?
The EFM32 Series 1 (i.e. Jade Gecko and Pearl Gecko) products contain a completely redesigned DMA that greatly improves throughput and reduces memory bus transfers.
The new linked list descriptor allows more flexible data transfer management.
Each descriptor has a link address which points to the next descriptor in the list. A descriptor may be removed from the Linked list by altering the Link address of the one before it to point to the one after it. Descriptor Linked lists are useful when handling an array of buffers for communication data. For example, a bad packet can be removed from a receiver queue by simply removing the descriptor from the linked list.
The new synchronization structure allows synchronization to occur between multiple DMA channels. For example, if DMA channel 1 should only move data after DMA channel 2 completes, a synchronization descriptor can be configured to perform this wait.
See the EFM32 Series 1 Reference Manual for more information.
How does programmable GPIO drive strength work on the EFM32 Series 1, and why can't I use the emlib GPIO_DriveModeSet function?
EFM32 Series 0 family members allow selection of GPIO drive strength via a DRIVEMODE field present in each of the GPIO_Px_CTRL registers. Options available are standard (6 mA), lowest (0.1 mA), high (20 mA), and low (1 mA) as shown below:
Note, of course, that the DRIVEMODE field, in conjunction with the GPIO_Px_MODEL and GPIO_Px_MODEH registers really only permit a binary selection of drive strength: either standard (6 mA), when PUSHPULL or one of the WIREDAND modes is selected, or one of the other DRIVEMODE encodings, when the PUSHPULLDRIVE or one of the WIREDANDDRIVE modes is selected.
Selection of a port drive strength is made easy by means with the emlib GPIO_DriveModeSet. Simply specify a port and the desired drive strength:
GPIO_DriveModeSet (gpioPortB, gpioDriveModeHigh);
The other enums for GPIO_DriveModeSet are gpioDriveModeLowest, gpioDriveModeLow, and gpioDriveModeStandard. As explained above, this allows a binary selection of drive strength when using the emlib GPIO_PinModeSet function. Consider pins 5 and 6 of port B when its DRIVEMODE is configured as above:
GPIO_PinModeSet (gpioPortB, 5, gpioModePushPull, 0);
GPIO_PinModeSet (gpioPortB, 6, gpioModePushPullDrive, 0);
In these examples, port B pin 5 is configured as an output with standard (6 mA) drive strength, while port B pin 6 is configured as an output with high (20 mA) drive strength. Again, note the binary selection of drive strength, either standard or the alternate selection specified by DRIVEMODE.
Recognizing this, the EFM32 Series 1 parts have simplified drive strength selection such that each port has a primary and alternate option. The GPIO_Px_CTRL registers have been modified to reflect this:
What is unchanged is the function of the GPIO_Px_MODEH and GPIO_Px_MODEL registers. Primary drive strength is used when PUSHPULL or one of the WIREDAND modes is selected, and alternate drive strength is used when PUSHPULLDRIVE or one of the WIREDANDDRIVE modes is selected.
However, what is primary vs. alternate drive strength can be confusing! Considering that the ALTDRIVESTRENGTH and DRIVESTRENGTH bit fields in GPIO_Px_CTRL default to 0 and, thus, weak drive (1 mA) on EFM32 Series 1, configuring a pin with the emlib GPIO_PinModeSet function as PUSHPULL or PUSHPULLDRIVE, for example, does not guarantee a specific drive strength as it did on EFM32.
To deal with this potential uncertainty, the GPIO_DriveStrengthSet function has been added to emlib. This function is similar GPIO_DriveModeSet, but it has an enumerated typedef for the binary driven strength options. So, to specify primary drive strength as strong (10 mA) and alternate drive strength as weak (1 mA) on EFM32 Series 1, the function call would be:
GPIO_DriveStrengthSet (gpioPortB, gpioDriveStrengthStrongAlternateWeak);
Naturally, the other enums would be gpioDriveStrengthWeakAlternateWeak, gpioDriveStrengthWeakAlternateStrong, and gpioDriveStrengthStrongAlternateStrong. It should be obvious that any ambiguity regarding primary and alternate drive strength on EFM32 Series 1 is resolved by making sure to specify each GPIO port's drive strength using GPIO_DriveStrengthSet BEFORE configuring any of the individual GPIO pins with the GPIO_PinModeSet function.
One last item to note is that GPIO_DriveModeSet and GPIO_DriveStrengthSet are mutually exclusive. When compiling emlib, GPIO_DriveStrengthSet is only compiled when the target is one of the EFM32 Series 1; GPIO_DriveModeSet will be unavailable. The reverse is true when the target is an EFM32 Series 0: GPIO_DriveModeSet is compiled and GPIO_DriveStrengthSet will be unavailable.
What is hibernate mode on the EFM32 Series 1?
Energy Mode 4 (EM4), which is also called shut off mode, is the lowest power mode for EFM32 Series 0 and EFM32 Series 1 devices. When the series 0 EFM32 device goes into EM4, all clocks are disabled and the chip is shut down except for the logic necessary to allow assertion of the nRESET pin to wake the device. Reset is the only means of recovery from EM4 on any Gecko (EFM32G) device.
The actual sources of reset have since been expanded on other EFM32 family members. All other members of the EFM32 series 0, as well as the EFM32 series 1, support wake via one or more user-designated GPIO pins. The pins available for wake are specific to a given device (EFM32 devices have a common subset available on all parts), but they all can trigger a reset in order to wake from EM4.
A further wake up source is available on devices with the Backup Real Time Counter (BURTC), where any enabled interrupt can trigger wake up. The wake request still triggers a reset, but now the wake up can be timed, which differs from either the assertion of nRESET or one of the user-designated GPIOs in response to some external event.
On the EFM32 series 1, EM4 is actually split into two related modes. Shut off mode is still present and behaves just as it does on the original EFM32 devices. nRESET or user-specified GPIO assertion wake up events are still available, as is the addition of wake from the new low-energy CRYOTIMER.
The new addition to EFM32 series 1 is called hibernate mode, and it is designated as EM4H while shut off is called EM4SH.
What differentiates hibernate from shut off mode is that extra logic is kept powered thus permitting wake up from other sources in addition to whatever shut off mode wake up sources are available.
On Jade and Pearl Gecko, the first two EFM32 series 1 devices, the sources for wake up from hibernate mode are the CRYOTIMER (also available in shut off), the Real Time Counter and Calendar (RTCC), monitored voltages that rise above or fall below user-specified thresholds (VMON), and temperature measurements that fall outside of a user-specified range (TEMPCHANGE).
Entry in hibernate mode (EM4H) follows virtually the same procedure as entry into shut off mode (EM4SH) with one distinct change. Writing the 0x2, 0x3, 0x2, 0x3, 0x2, 0x3, 0x2, 0x3, 0x2 sequence to the EM4ENTRY bit field in the EMU_EM4CTRL register places the device in hibernate mode when the EM4STATE bit is set; otherwise, the device enters shut off mode as usual. See the register and bit description below:
Regardless of the device, the emlib EMU_EnterEM4() function handles EM4 entry no matter whether shut off or hibernate mode is selected. Examination of the source code for EM4_EnterEM4() reveals that the EM4ENTRY write sequence is done in such a way that the initial value of the EM4STATE bit is retained. So, entering hibernate mode is simply a matter of setting the EM4STATE bit, then calling the EM4_EnterEM4() function. If EM4STATE remains at its reset value of 0, then shut off mode is entered instead.