When using a Low Energy Peripheral (one clocked by the LFB or LFA clocks) with Delayed Synchronization, where the Low Frequency clock is selected to be HFCORECLK/2, is it necessary to monitor the SYNCBUSY register between subsequent asynchronous register writes or reads?
No. In this case, no synchronization with the Core clock domain is necessary, since both the peripheral and the core are being driven by the same clock, and thus they are always synchronized.
The value of this bit may be indeterminate when the core and LF clocks are the same, so polling this bit should be avoided.
Additionally, be mindful of the HFCORECLKLE/HFCLKLE frequency limitations, as noted in this article: http://community.silabs.com/t5/32-bit-MCU-Knowledge-Base/Maximum-HFCORECLKLE-HFCLKLE-frequency-and-HFLE-WSHFLE/ta-p/140458
For most devices, the maximum LE clock is 16 MHz, although it is 12 MHz on some devices. See the table in the article for more details.