What is the usage of DPLL?


The Digital Phase-Locked Loop (DPLL) uses the HFRCO to generate a clock as a ratio of a reference clock source.

The reference clock source (FREF) can be HFXO, CLKIN0, LFXO, or USHFRCO (if available).

Output frequency = FREF*(N+1)/(M+1), where N and M are 12-bit values in CMU_DPLLCTRL1 register.

The DPLL is not available on EFM32xG1 and EFR32 devices.


Code example on EFM32PG12:



// Enable LFXO and wait it ready, use as DPLL reference clock
CMU_OscillatorEnable(cmuOsc_LFXO, true, true);

// Setup target HFRCO frequency, factor N and M 
CMU_DPLLInit_TypeDef dpllInit = CMU_DPLL_LFXO_TO_40MHZ; dpllInit.frequency = 36864000; dpllInit.n = 2249; dpllInit.m = 1; // CMU_DPLLLock() will update flash wait state and SystemCoreClock for target HFRCO frequency if (!CMU_DPLLLock(&dpllInit)) { // DPLL lock failed while (1); }



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