Question

What is the maximum ADC clock frequency on EFM32 Series 1

Answer

The maximum ADC clock frequency on EFM32 Series 1 is derived from below formula.

Tconv= (Tacq+ (N + 1) x Tadc_clk_sar) x OVSRSEL

 

Where:

The conversion time Tconv is 1 us for sampling at 1 Msps

The minimum acquisition time Tacq for sampling at 1 Msps and typical input loading is 187.5 ns

The maximum conversion resolution N is 12

Tadc_clk_sar is the ADC clock cycle

The oversampling is disabled and OVSRSEL is equal to 1

 

 

Tadc_clk_sar = (Tconv - Tacq) / (N +1) = (1 us - 187.5ns) / (12 + 1) = 0.0625 us

ADC clock frequency = 1 / Tadc_clk_sar = 16 MHz

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