For EFM32PG1, the USART has a 15-bit integral and 5-bit fractional clock divider to allow the USART clock to be controlled more accurately than what is possible with a standard integral divider.
However, the fractional part of divider can only use for asynchronous operation (UART), if the fractional part is used on synchronous operation (e.g. SPI master), it could cause half clock cycles to exceed a specified limit and thus potentially violate specifications for the slave device could tolerate. Especially for high speed use case that need a very low divider value.
In order to avoid this kind of issue, in emlib, the fractional part of the clock divider for clock generation is suppressed in the function USART_BaudrateSyncSet(), thus only the bit-rate that equals HFPERCLK/2 divided by an integral without remainder is available.
Suppose the HFCLK is 38.4MHz, and HFPERCLK is 19.2MHz which is prescaled HFCLK, what the available bit-rate of SPI master mode are 19.2/2MHz, 19.2/4 MHz, etc.
In some special situations, the fractional clock division may be useful even in synchronous mode (especially for low speed use case where a very high divider value is needed. In that case, the high/low asymmetry of the SPI clock phenomena is not heavy), but in those cases the bit-rate must be directly adjusted with the API of USART_BaudrateCalc().