What are the points to be kept in mind while powering IOVDD through DC-DC as far as debug connections are concerned?
There is a difference between the startup configuration in EFM32PG1 and EFM32PG12. Under the startup configuration in EFM32PG1, the bypass switch is always on while in the case of EFM32PG12, the DC-DC is not configured -
In this case if IOVDD is connected to DC-DC's output instead of VDD, then during startup, IOVDD will be at 0V until the DC-DC powers up through firmware. But, one cannot debug the part without connecting the Vtarget pin to IOVDD. The DC-DC is completely under software control. It boots up in the off state and must be turned on by software. To have the DC-DC always boot up at cold start before the CPU would require a complete redesign of the DC-DC and would cause other issues. Not everyone wants to use the DC-DC, or use it in the same way. The SWIO connections are pin-shared with other GPIO and we cannot afford to have dedicated SWIO pins or a dedicated VIO for the SW.
So, what can be done?
A couple of solutions are available at the moment-
1. Add an external 2 pin jumper to short 3.3V to VDCDC, connect the debugger, program the part, then remove the jumper. But this wouldn’t support the case where some circuitry powered from VDCDC couldn’t exceed 1.8V +10%.
2. Build an adapter board that plugs into the Segger J-link 20-pin header on one side and provide a 10-pin header with 1.8V out to connect to a target board that needs 1.8V.