A few customers want to connect the GPIOs of EFR32 chips to external 1.8V MCU's interface other than 3.3V. Thus they connect the chip's IOVDD to 1.8V power supply other than normal 3.3V power supply. The problem is raised up how to connect the chip's debug port to the BRD4001A mainboard. This KBA describes the configuration of mainboard and the connection between the mainboard and chip's custom radio board.
1) The mainboard configuration and debug adapter board plugged:
Since the interface voltage is 1.8V other than 3.3V, the power switch on mainboard should be configured to USB position which let the customer radio board self powered. Otherwise there will be power conflict between mainboard 3.3V domain and customer radio board interface1.8V domain.
2) How the mainboard take the reference voltage and shift the signals to the standard 3.3V logical:
Figure 2 shows that the VMCU(Come from custom radio board's VDCDC of 10-pin Mini Simplicity Debug connector) on mainboard is mirrored by VMCU_BUF. Then the VMCU_BUF is used as reference voltage for level shifter, and it will shift the UART0 and PTI signals as Figure 3 shows.
Figure 4 shows that the level shifting for SWD signals, its reference also come from custom radio board's reference, because the VTARGET will be the same with DH_VTARGET when configure the debug mode to Debug Out mode, and the DH_VTARGET is connected to VDCDC of 10-pin Mini Simplicity Debug connector of custom radio board.
3) Power configuration on custom radio board:
The above custom radio board power configuration is typical for 1.8V logical power level. Actually the debug port reference level can be set to any value between 1.8V and 3.3V by adjusting the DC-DC output voltage.
EFM32/EFR32/EZR32 devices' USART peripherals contain either a 15-bit (Series 0 devices) or a 20-bit (Series 1 devices) fractional clock divider, which contains both an integer part and a fractional part to allow for the clock to be controlled more accurately than what is possible with a standard integer divider.
The baudrate is defined by the following equation:
baudrate = f_hfperclk / (oversample * (1 + (USARTn_CLKDIV / 256)))
Conversely, the formula for determining the USARTn_CLKDIV value, given a desired baudrate, is:
USARTn_CLKDIV = 256 * ((f_hfperclk / (oversample * baudrate_desired)) - 1)
For example, for a peripheral clock frequency of 19 MHz, an oversample value of 16x, and a desired baudrate of 19200, the result is:
USARTn_CLKDIV = 256 * ((19000000/ (16 * 19200)) - 1) = 15577 ( 0x00003DC9)
To apply this value to the USART, it is important to set it directly to the USARTn_CLKDIV register. This value does not go in the DIV bitfield in this register (which would require shifting). No shifting is applied when writing this register. So, for example, to write this clock divider to USART4, you would write the following:
USART4->CLKDIV = 0x00003DC9; // 19200 baudrate with 16x oversample and 19 MHz peripheral clock