Question

How do I use the alternate excite pin for LESENSE excitation in series 1 devices?

Answer

There are a total of 16 channels in the LESENSE peripheral, and there are 8 alternate excitation pins. Each alternate excite pin is mapped to Channel X and Channel X + 8 with 0 < X < 8. For pin mapping of each device, please refer to the Alternate Functionality Overview section in the device's datasheet.

In order to use the alternate excitation pin, add the following sequence into the LESENSE initialization routine:

1. Set ALTEX to true in the LESENSE_CHx_INTERACT register (x being the channel number you want to configure).

2. Set ALTEXMAP to ALTEX in the LESENSE_CTRL register.

3. Enable the corresponding channel pin (CHxPEN) and Altex pin (ALTEXxPEN) in LESENSE_ROUTEPEN register.

4. Configure the LESENSE_ALTCONFIG register for desired setting (check register description in the reference manual for more information).

5. Make sure the corresponding GPIO pin for alternate excite is set to push-pull output if the excitation type is logical low or logical high.

You should be able to see the excitation pulse in the alternate excite pins with these configuration added.

An example of using LESENSE excitation pin is attached in this article. The example runs on an EFR32MG12 starter kit and the excitation pulse is on PA8, which is the alternate excitation pin for LESENSE channel 0 on EFR32MG12. The code added to enable alternate excite is:

  LESENSE -> CTRL |= LESENSE_CTRL_ALTEXMAP_ALTEX;
  LESENSE -> ROUTEPEN |= LESENSE_ROUTEPEN_ALTEX0PEN | LESENSE_ROUTEPEN_CH0PEN;
  LESENSE -> CH[0].INTERACT |= LESENSE_CH_INTERACT_ALTEX;
  LESENSE -> ALTEXCONF |= LESENSE_ALTEXCONF_IDLECONF0_LOW;

Introduction

EFR32 devices allow the JTAG TDI/TDO pins to be used for other functions when not needed for JTAG debugging. Under certain circumstances, such as an unexpected reset during debug, control of these pins can unexpectedly be transferred to the debug peripheral. On Series 2 devices this happens more frequently due to changes in the reset topology. In such cases, the device must be reset again to regain normal control over the pins.

Background

JTAG and SWD

EFR32 supports debugging through either the JTAG or the SWD protocol. The JTAG protocol is an industrial standard for testing and verifying PCBs that utilizes 4 pins; TCK, TMS, TDI and TDO. SWD is an ARM proprietary protocol that is interoperable with a JTAG test environment, but utilizing only two pins, the TCK and TMS pins.

Debug Port

The Serial Wire/JTAG Debug Port (SWJ-DP) is responsible for implementing both the JTAG and the SWD interface. The SWJ-DP also facilitates for switching between the two protocols on demand.

The SWJ-DP allows a designer to allocate the JTAG TDI and TDO pins to other functionality, such as GPIO, when only using the SWD interface. 

On startup the SWJ-DP will, for compatibility reasons, default to JTAG mode. In order to switch to SWD mode, a debugger will have to transmit a specific initialization sequence on the TCK and TMS pins. This initialization sequence is designed such that it will not affect any JTAG devices on the same bus.

JTAG-on-demand

JTAG-on-demand is an EFR32-specific feature that allows an EFR32 device to appear as defaulting to SWD mode. This means that the TDI and TDO pins are allocated as normal GPIO at startup instead of being allocated to the debug interface.

JTAG-on-demand will reallocate the TDI and TDO pin to the debug interface when the SWJ-DP is in JTAG mode and detects JTAG traffic. Once JTAG-on-demand has been activated, it will not be deactivated until the next full reset of the chip (and debug interface).

JTAG-on-demand can be overridden by writing to the GPIO.DBGROUTEPEN register. Attempting to write the relevant bits while the debug circuitry is active will cause a BusFault on Series 2 devices.

Series 2 reset topology

EFR32 Series 2 devices have a different reset topology than EFR32 Series 1 devices. The most notable change is that in Series 2 devices the debug interface is reset on assertion of the RESETn pin.

Error Conditions

If anything except the full SWD initialization sequence is received by the EFR32 on the debug interface while the SWJ-DP is in JTAG-mode, JTAG-on-demand will activate and transfer control of the TDI and TDO pins to the SWJ-DP.

When control of the pins has been transferred, the pins cannot be used in any other function, including normal GPIO, SWO or ETM Trace.

There are two scenarios in which loss of control over TDI and TDO is likely to occur:

• If the EFR32 is reset in a way that causes the debug interface to be reset while there is an active SWD debug session. For Series 2 device, this includes reset via the RESETn pin. The debug adapter will be unable to detect this reset in all circumstances, causing the debug adapter to continue communicating over SWD, activating the JTAG-on-demand feature.
• If the debug adapter attempts to initialize the SWD connection before the EFR32 has fully exited reset so that the SWD initialization sequence is not registered. This causes JTAG-on-demand to activate when verifying the connection as required by ARM.

While it is possible for this to occur on EFR32 Series 1 devices, it is a lot easier to trigger on Series 2 devices due to the change in reset topology. It is also not possible to override the JTAG-on-demand feature on Series 2 devices, contrary to Series 1 devices where this is possible.

Consequences

When JTAG-on-demand is activated on an EFR32 Series 2 device, the following will happen

• SWO will stop working
• ETM Trace will stop working
• Loss of control over GPIO pins PA3/PA4

For Silicon Labs development kits, the following are features that can be affected depending on what is connected to PA3/PA4:

• VUART
• Simplicity Studio Code Correlation
• External SPI Flash
• VCOM Flow Control (CTS always high)
• Button stuck high

Workaround

Once the condition occurs, the only known workaround is to disconnect all active debug sessions, reset the target through the RESETn pin or toggling power.

Glossary