When flash locking a Precision 32 device (SiM3U, SiM3C, SiM3L), J-link debug adapters, and specifically J-link commander can no longer connect to, erase, or debug the device. After attempting to connect to a device, the following response is received from J-link commander:
J-Link connection not established yet but required for command.
Connecting to J-Link via USB...O.K.
Firmware: Silicon Labs J-Link OB compiled Jan 18 2019 14:09:54
Hardware version: V1.00
S/N: 440124222
VTref = 3.259V
Target connection not established yet but required for command.
Device "CORTEX-M3" selected.
Connecting to target via SWD
Found SW-DP with ID 0x2BA01477
Scanning APs, stopping at first AHB-AP found.
AP[0] IDR: 0x24770011 (AHB-AP)
AHB-AP ROM: 0xE00FF000 (Base addr. of first ROM table)
CPUID reg: 0x00000000. Implementer code: 0x00 (???)
Unknown core, assuming Cortex-M0
Found Cortex-M0 r0p0, Little endian.
**************************
WARNING: Identified core does not match configuration. (Found: Cortex-M0, Configured: Cortex-M3)
**************************
The SiM3 devices require a specific series of commands, unique to these devices, to connect and erase when the parts are flash locked. The procedure is not performed automatically by J-link commander. The procedure is as follows:
How the SiM3Uxxx is marked on the top of the package?
Answer
Looking at the image attached to this article.
for the device SiM3U167, there are 4 lines of text and/or symbols as follows:
The first line reads “SiM3U167” is the part number.
The second line is the revision and package type.
The first character, e.g. "B', represent the device revision.
the followed 2 characters after '-' means package, GM - QFN (no-lead) and GQ - QFP (with leads)
The third line reads, in this example, “1031BCS701”.
The first 4 numbers represent the date code in YYWW format where YY = year, WW = work week. In this example, the device is dated 2011, work week 31.
The character after the date code, e.g. “B”, represents the device revision.
The 5 characters after the device revision, e.g. “CS701”, are trace code.
The fourth line contains an oval with an “e3” followed by the abbreviation “TW”.
The “e3” in an oval is the JEDEC marking used to designate the category of Pb-Free terminal finish used on the device. In this case, “e3” = Sn or Matte Tin.
The “MY” refers to the where the device was manufactured which in this case is Malaysia
For the device Sim3U1*4, the mark is different, there is no information of second and fourth lines that present in the marking.
How do I read the link register (LR) for an ARM Cortex M series device?
Answer
Link Register
On an ARM Cortex M series device, the link register (LR or R14) is a core register that stores the return address, such as when making a function call. In the case of an exception, the return address is pushed onto the stack by hardware and the LR is set to EXC_RETURN (0xFFFFFFF1, 0xFFFFFFF9, or 0xFFFFFFFD).
When debugging exceptions such as hard faults, reading the LR is necessary to determine which stack pointer was used when the exception occurred.
Reading the Link Register
ARM provides CMSIS functions to read and write the main stack pointer (MSP). These can be found in cmsis_gcc.h for the GCC compiler.
Reading the LR is similar to reading the MSP except that the MOV instruction is used instead of the MRS instruction.
To read the LR from C code using GCC, use the following function:
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
/**
\brief Get Link Register
\details Returns the current value of the Link Register (LR).
\return LR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
{
register uint32_t result;
__ASM volatile ("MOV %0, LR\n" : "=r" (result) );
return(result);
}
Then in code, call __get_LR():
__get_LR();
This function generally copies the LR to a register and is dependent on the compiler calling convention. In simple cases, the LR is copied to R3. However in C programs, the LR can be assigned to a local or global variable.
In the SiM3L reference manual, the following statement is made in regards to enabling the temperature sensor:
The internal voltage reference can be enabled using the VREFOUTEN bin in the CONTROL register. When enabled, the internal voltage reference node is available to any analog peripherals which have a VREF input.
However, when attempting to write this bit in the VREF0_CONTROL register, the value is not set!
Answer
The VREF needs to be clocked by the APB, which is not enabled by default. The reference manual does not mention that there is an enable bit for this, but it does exist as the MISC0CEN bit in the CLKCTRL0_APBCLKG1 register. This bit has the following description:
Miscellaneous 0 Clock Enable. 0: Disable the APB clock to the VMON0, LDO0, EXTOSC0, LPOSC0, RTC0 and RSTSRC modules. 1: Enable the APB clock to the VMON0, LDO0, EXTOSC0, LPOSC0, RTC0 and RSTSRC modules
This bit, despite not mentioning it here, enables the clock to the VREF registers.
You can enable this using the following SiM3L API statement:
In the Precision 32 IDE, for SiM3xx devices, semi-hosting is used as a way to send information from the device to the host, such as re-directing printf statements to the debug console. This is enabled by default in Precision 32 projects. Unfortunately, when this feature is enabled, the debugger is required to be connected to the device in order for the program can run. This is because this semi-hosting procedure requires some level of negotiation with the debugger. More information on semi-hosting is available in this article: http://community.silabs.com/t5/32-bit-MCU-Knowledge-Base/What-is-Semihosting/ta-p/112897
In order to disable semi-hosting, navigate to [Project] > [Properties] > [C/C++ Build] > [Settings] > [MCU Linker] > [Target], and change the "Use C Library" setting from "Redlib (semihost)" to a different library that does not include semihosting.
In Precision32 MCUs, there are two classes of interrupt priority: "Preempt Priority" and "Subpriority". Interrupts of like preempt priority cannot interrupt each other, and this is the default state of the peripheral interrupts. Subpriority is used to determine service order when two interrupts of like preempt priority are both pending and the CPU is available to service at their preempt priority level.
See section 4.3 in the SiM3U/C reference manual for more information.
In some of the documentation under the Soldering Information section it states, "Place as many and as small as possible vias underneath each of the solder patches under the ground pad," does this mean to put filled or covered vias?
Answer
The vias should be filled. If they are left open, the solder has the potential to wick into the holes and cause random fallout due to the part skewing on the PCB.
32-bit Knowledge Base
De-bricking or unlocking a Precision 32 device in J-link commander
Problem:
When flash locking a Precision 32 device (SiM3U, SiM3C, SiM3L), J-link debug adapters, and specifically J-link commander can no longer connect to, erase, or debug the device. After attempting to connect to a device, the following response is received from J-link commander:
Solution:
The SiM3 devices require a specific series of commands, unique to these devices, to connect and erase when the parts are flash locked. The procedure is not performed automatically by J-link commander. The procedure is as follows:
A j-link commander script has been attached to this article to perform these commands. The usage is as follows:
JLink -If SWD -Speed 4000 -Device Cortex-M3 -CommanderScript <path>\SIM3_deBrick.jlink
SiM3Uxxx part marking
32-bit Device Availability and Longevity
Question
I am concerned about the device I am using being discontinued (end of life or EOL). Is there information about product life anywhere on your website?
Answer
The following page on our website lists the minimum longevity of our 32-bit MCU devices:
http://www.silabs.com/products/mcu/32-bit/longevity-commitment
Similarly, for our 32-bit Wireless MCU devices see:
http://www.silabs.com/products/wireless/longevity-commitment
For devices not listed, please inquire with your local sales representative:
http://www.silabs.com/buysample/pages/contact-sales.aspx?view=map
How to read the link register (LR) for an ARM Cortex M series device
Enabling the Temperature Sensor on SiM3L devices
Disabling Semi-hosting on Precision32 devices
Precision32 Interrupt Priority
Keil uVision v5 support for SiM3
Layout and Soldering Information
SiM3L1xx RTC oscillator robustness