Answer

Looking at the image attached to this article.

for the device SiM3U167, there are 4 lines of text and/or symbols as follows:

• The first line reads “SiM3U167” is the part number.
• The second line is the revision and package type.
• The first character, e.g. "B', represent the device revision.
• the followed 2 characters after '-' means package, GM - QFN (no-lead) and GQ - QFP (with leads)
• The third line reads, in this example, “1031BCS701”.
• The first 4 numbers represent the date code in YYWW format where YY = year, WW = work week. In this example, the device is dated 2011, work week 31.
• The character after the date code, e.g. “B”, represents the device revision.
• The 5 characters after the device revision, e.g. “CS701”, are trace code.
• The fourth line contains an oval with an “e3” followed by the abbreviation “TW”.
  • The “e3” in an oval is the JEDEC marking used to designate the category of Pb-Free terminal finish used on the device. In this case, “e3” = Sn or Matte Tin.
  • The “MY” refers to the where the device was manufactured which in this case is Malaysia

For the device Sim3U1*4, the mark is different, there is no information of second and fourth lines that present in the marking.

Answer

Link Register

On an ARM Cortex M series device, the link register (LR or R14) is a core register that stores the return address, such as when making a function call.  In the case of an exception, the return address is pushed onto the stack by hardware and the LR is set to EXC_RETURN (0xFFFFFFF1, 0xFFFFFFF9, or 0xFFFFFFFD).

When debugging exceptions such as hard faults, reading the LR is necessary to determine which stack pointer was used when the exception occurred.

Reading the Link Register

ARM provides CMSIS functions to read and write the main stack pointer (MSP).  These can be found in cmsis_gcc.h for the GCC compiler.

Reading the LR is similar to reading the MSP except that the MOV instruction is used instead of the MRS instruction.

To read the LR from C code using GCC, use the following function:

#define __ASM __asm /*!< asm keyword for GNU Compiler */ 
#define __INLINE inline /*!< inline keyword for GNU Compiler */ 
#define __STATIC_INLINE static inline 

/** 
\brief Get Link Register 
\details Returns the current value of the Link Register (LR). 
\return LR Register value 
*/ 
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void) 
{ 
  register uint32_t result; 

  __ASM volatile ("MOV %0, LR\n" : "=r" (result) ); 
  return(result); 
} 

Then in code, call __get_LR():

__get_LR();

This function generally copies the LR to a register and is dependent on the compiler calling convention.  In simple cases, the LR is copied to R3.  However in C programs, the LR can be assigned to a local or global variable.

Answer

The VREF needs to be clocked by the APB, which is not enabled by default. The reference manual does not mention that there is an enable bit for this, but it does exist as the MISC0CEN bit in the CLKCTRL0_APBCLKG1 register. This bit has the following description:

Miscellaneous 0 Clock Enable.
0: Disable the APB clock to the VMON0, LDO0, EXTOSC0, LPOSC0, RTC0 and
RSTSRC modules.
1: Enable the APB clock to the VMON0, LDO0, EXTOSC0, LPOSC0, RTC0 and
RSTSRC modules

This bit, despite not mentioning it here, enables the clock to the VREF registers.

You can enable this using the following SiM3L API statement:

SI32_CLKCTRL_A_enable_apb_to_modules_1(SI32_CLKCTRL_0, SI32_CLKCTRL_A_APBCLKG1_MISC0);

Answer

uVision 5 does support SiM3 devices, however the legacy support pack must be installed: http://www2.keil.com/mdk5/legacy

Answer

The vias should be filled. If they are left open, the solder has the potential to wick into the holes and cause random fallout due to the part skewing on the PCB.

Answer

The robust duty cycle range is defined in the datasheet and is 25% to 55%. The low threshold is 55% and the high threshold is 60%.