I'm using the SMBUS0 on a 8051F582 device, configured as master and using Timer1 for setting the SCL frequency.
If I want to generate a reset on the bus i.e. by pulling the SCL line low for >35 ms (that is what my slave specifies). What are my options?
1) Reconfigure the crossbar so I manually can set the SCL low? How do I do this without disturbing all my other interfaces (UART, CAN etc.)? What order do I need to set relevant register for a "glitch" free reconfiguration? My understanding is that it is always possible to read but not write to a pin if it is assigned by the crossbar to a resource.
2) The data sheet hints (page 246): "The SMBus interface is stalled while SI is set; thus SCL is held low, and the bus is stalled until software clears SI.". Perhaps I can manually set the SI bit in SMB0CN and with a separate "RESET" flag indicate that the ISR shall not clear the SI. Wait for 35 ms, clear the "RESET" flag and the SI bit. Any pitfalls in this logic?
3) Other ideas?
Thanks!
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2) The data sheet hints (page 246): "The SMBus interface is stalled while SI is set; thus SCL is held low, and the bus is stalled until software clears SI.". Perhaps I can manually set the SI bit in SMB0CN and with a separate "RESET" flag indicate that the ISR shall not clear the SI. Wait for 35 ms, clear the "RESET" flag and the SI bit. Any pitfalls in this logic?
doable BUT you do not want to hang in an ISR for that long..
an idea for you to think through
in main disable the the SL interrupt, set SL set a flag start a timer, in the timer interrupt disable the timer clear the flag and enable the SL interrupt
Correct Answer
1
For sure. Don't wanna hang 35 ms in the ISR. To clarify, I'm hanging around outside the ISR. Thanks for your help!
SMBus reset options
Hello!
I'm using the SMBUS0 on a 8051F582 device, configured as master and using Timer1 for setting the SCL frequency.
If I want to generate a reset on the bus i.e. by pulling the SCL line low for >35 ms (that is what my slave specifies). What are my options?
1) Reconfigure the crossbar so I manually can set the SCL low? How do I do this without disturbing all my other interfaces (UART, CAN etc.)? What order do I need to set relevant register for a "glitch" free reconfiguration? My understanding is that it is always possible to read but not write to a pin if it is assigned by the crossbar to a resource.
2) The data sheet hints (page 246): "The SMBus interface is stalled while SI is set; thus SCL is held low, and the bus is stalled until software clears SI.". Perhaps I can manually set the SI bit in SMB0CN and with a separate "RESET" flag indicate that the ISR shall not clear the SI. Wait for 35 ms, clear the "RESET" flag and the SI bit. Any pitfalls in this logic?
3) Other ideas?
Thanks!
2) The data sheet hints (page 246): "The SMBus interface is stalled while SI is set; thus SCL is held low, and the bus is stalled until software clears SI.". Perhaps I can manually set the SI bit in SMB0CN and with a separate "RESET" flag indicate that the ISR shall not clear the SI. Wait for 35 ms, clear the "RESET" flag and the SI bit. Any pitfalls in this logic?
doable BUT you do not want to hang in an ISR for that long..
an idea for you to think through
in main disable the the SL interrupt, set SL set a flag start a timer, in the timer interrupt disable the timer clear the flag and enable the SL interrupt
For sure. Don't wanna hang 35 ms in the ISR. To clarify, I'm hanging around outside the ISR. Thanks for your help!