Why does the datasheet say the Fast Mode (400 KHz Class) SMBus has a maximum operating frequency of 255 kHz?
The SMBus peripheral is internally clocked at 3 times the target bit rate and generates clock low from 1 clock cycle and clock high from 2 clock cycles.
The SMBus 400 kHz fast speed specifies clock low must be at least 1.3 us. So 1/(3x1.3us) = 256 kHz. If you set the SCL frequency to higher than 256 kHz, then the clock low time will be less than 1.3 us and violate the spec.
In practice, many I2C devices will work fine above 256 kHz, but the device will be in violation of the timing requirements, so full compatibility can't be guaranteed for strict systems.
I am trying to use ADC on the C8051F35x and am having problems figuring out how the offset DAC works.
First of all, I am not sure if the offset DAC is added to or subtracted from the AIN+ and AIN- inputs such that it has the effect of level-shifting, is applied to only one input, or even if its doing the opposite on both inputs (half the value subtracted from AIN+ and half value added to AIN-, which would cancel any offset completely.
Also, application note AN217, which has the same block diagram as the 'F35x datasheet...
...shows that the offset should be applied before the gain, but in my tests it seems to be done afterwards.
From what I can tell, the offset voltage is substracted after the amplification. Is this expected behavior, or am I doing something wrong?
As the customer has noted, there appears to be a notable difference in how the offset DAC behaves relative to the PGA, and, in this case, the customer is correct: the offset DAC operates after the PGA. So, for starters, the block diagram above should be modified as follows:
Furthermore, consistent with the customer's experiments, the ODAC output is subtracted from AIN+ and added to AIN- as a signed value, where bit 7 and bits [6:0] of the ADC0DAC register represent the sign value (0 = positive, 1 = negative) and the magnitude, respectively.
When trying to do isochronous transfers with the USB Peripheral Driver Library, you may notice that the library only supports isochronous transfers on Endpoint 3 even though the device's datasheet says endpoints 1-3 support isochronous transfers.
The device does support isochronous transfers on endpoints 1 through 3, but the library was only designed to support isochronous transfers on endpoint 3 by default. All Silicon Labs designs use endpoint 3 for isochronous transfers, so the library was built around this as well as with the idea of keeping the code simple in mind. The library can be modified to support isochronous on other endpoints, but the library does not support this out of the box.
I am trying to reproduce the current consumption numbers specified in the datasheet of an EFM8 device. How do I make sure that I am using the same settings as the numbers in the datasheet?
Provided with Simplicity Studio is a set of software examples that demonstrate how to use the device's various peripherals. One of these examples is PowerModes and shows how to put the device into its various low power states. In Simplicity Studio, this code is listed under Software Examples when you have your device selected.
While running the TestPanel example which included in the USBXpress 4 SDK v4.0.3 on C8051F340 MCU, the device can be enumerated as a USBXpress Device viewing from the Windows Device Manager, however, it failed to start the Host application TestPanel.exe, what would cause the issue as below?
This is caused by incorrect USBXpress driver version installed on your machine if you are not using the USBXpress driver that is included in the same SDK version.
To solve the issue, uninstall the existing driver of the USBXpress Device, and then re-install the corresponding driver included in the USBXpress SDK where you are running the USBXpress example.
For the USBXpress SDK v4.0.3 mentioned above, the driver version is 184.108.40.206 with driver date of 4/8/2013.
Can we use EFM8 STK on board JLink debugger to program C8051 device?
Yes, this is possible.
The steps as follows:
1. Upgrade the adapter firmware on the EFM8 STK to latest version 0v15p3b761. Two ways to update and verify the adapter firmware:
a. Connect the STK to PC and start Simplicity Studio V4, Select you STK in device view. Clicking on Adapter Firmware Version->Change->Adapter Configuration, that allows you to update the Jlink adapter's firmware. You can see firmware version next to "Adapter Firmware Version" in launcher view.
b. Start the Simplicity Commander and connect Jlink adapter of STK, under the Kit->Update Kit->Installation package, user can select fimrware package by clicking on Browse button, Then click on Install Package button to install it. The firmware version is displayed on the Kit->Kit Information->Firmware version.
2. Connect the VTARGET, C2D, C2CK and GND signals of the Debug Connector on the EFM8 Starter Kit to the target .
3. Make sure target MCU powered up.
4. Change STK Debug Mode to Debug Out. Both Simplicity Studio and Simplicity Commander can do this job.
5. Using Segger JLink tool to program the blinky hex image file to C8051F380 and run the code:
SEGGER J-Link Commander V6.17a (Compiled Jul 10 2017 17:13:16) DLL version V6.17a, compiled Jul 10 2017 17:12:41 Connecting to J-Link via USB...O.K. Firmware: Silicon Labs J-Link OB compiled May 19 2017 10:18:02 Hardware version: V1.00 S/N: 440033288 VTref = 3.250V Type "connect" to establish a target connection, '?' for help J-Link>device C8051F380 J-Link>connect Please specify target interface: C) C2 (Default) TIF> Specify target interface speed [kHz]. : 1000 kHz Speed> Device "C8051F380" selected. Connecting to target via C2 DevID, DerivID: 0x28, 0xD0 Core: CIP-51 (8051 compatible) Device series: C8051F38x series device CPU supports 4 code breakpoints Flash infos: 512 byte sectors, 126 sectors, all sectors unlocked Memory zones: C CODE I IDATA D DDATA X XDATA DSR DSR C2 C2 8051 (EFM8) identified. J-Link>loadfile F38x_Blinky.hex Downloading file [F38x_Blinky.hex]... O.K. J-Link>g J-Link>
Note: The Flash Programmer integrated in the Simplicity Studio has problem to program C8051F380 through the EFM8 STK on-board JLinker debugger. So here we choose Jlink commander tool to program C8051 devices.
Please also check the Segger website to see what C8051Fxxx part was supported by the JLink debugger.
For 8-bit MCU like EFM8UB2, a port pin isavailable on crossbar, do I need to enable crossbar if a port pin work as general purpose GPIO (non peripheral mode)?
For port pin is available on crossbar, if you need to control it's level through the Px.x latch value, you need to enable the crossbar.
Take the EFM8UB2 as example, you could see what port pin was available on crossbar in figure 11.4 on page 83 of the reference manual.
The port I/O cell block diagram shown in figure 11.2 on page 79 of reference manual.From the below diagram, we can know once the crossbar is disabled, the Px.x latch value wont' take effects on port pin.
What is the difference of GPIO structure on Silicon Labs MCU families.
5V tolerance of GPIO pins on Silicon Labs MCU families as followsType A:
Pins are tolerant of the IO power supply voltage plus 2.5V, so they are 5V tolerant with a 3.3V supply. When the pin voltage rises more than 2V above the supply, the leakage currents from the pin to the supply and from the pin to ground will increase with voltage. When the power supply is 0V, the applied pin voltage can be as high as 3.3V at room temperature with moderate leakage; but at that voltage, the leakage can be very high at elevated temperature.
Devices: EFM8UB1, C8051F86x.etc
There is a statement in EFM8LB1 spec that pin leakage current is in the range of [-1.1 4] uA . Does this leakage current affects ADC result of external signal?
Correct, the leakage mainly dominated by the ESD protection circuit for the port structure. It may flow in or out of the device. The leakage current is strongly sensitive to the temperature.
Let us assume 100nA leakage, and output impedance for source signal to be measured is 10k ohm. Then the measurement error caused by the leakage likes an offset error of ADC result. This example gets 100nA*10kOhm = 1mV voltage offset (measured) on the pin.
Under condition that ADC is configured as 2.5V VFS and 12-bit resolution. Then we have 1 LSB equals to be about 2.5V/4096 = 610uV
Then the 10k Ohm resistance of external source signal to be measured would see 1 LSB offset error as 1mV>610uV.
Related KBA: Comparator Input Leakage
What is the width of the pins on the TQFP-48 package on EFM32HG devices? This is not listed as a dimension in tables 4.4 (package specifications).
Firstly, page 59, Figure 5.1 does show the recommended landing patterns for this device's pins as 1.6 x 0.3 mm. So, it's reasonable to expect the pin width to be, at most 0.3 mm.
In table 4.4, we can also derive the pad with by examining the distance between the edges of adjacent pins (0.2 mm, T, U, V, Z) and the pitch width (the distance between the centers of pins (0.5 mm). The pitch width should be equal to (1/2 pin width) * 2 + pin separation. So pin width + 0.2 mm = 0.5 mm, so pin width equals 0.3 mm.
Examining a TQFP-48 device here with a microscope, I observe that the pins indeed do seem larger than the gaps between them, so 0.3 mm should be the correct number for the pin width, and 0.2 mm for the pin gaps.