Is it possible to detect a break condition on the UART RX line when using the EFM8 UART0? If so, is there a software example that demonstrates this?
While the EFM8 UART0 module itself does not support break detection, and we do not have any software examples that demonstrate this exact application, it should be fairly straightforward to modify one of our existing examples for the pulse counter array (PCA) to detect a break condition.
By externally routing the RX data line to a separate MCU pin (on your PCB) and using the crossbar to select that pin as a PCA input, you can use the input capture mode of the PCA to detect the break condition on the line. A good starting point for this application would be out firmware example "EFM8SB1 PCA0 Capture Input," which you can access through Simplicity Studio under the EFM8SB1 software examples.
Can the BLDC example be applied to a synchronous reluctance motor? https://www.silabs.com/products/development-tools/mcu/8-bit/sensorless-bldc-motor-reference-design
The design of synchronous reluctance motors is significantly different from brushless DC motors, so the reference design will not be useful for this application.
How can I generate a PWM waveform that has variable frequency (between 9 kHz and 12 kHz with at least 200 steps in between) using the CLU? Can I use timer 0 for this purpose? How do I control the Duty Cycle of the PWM waveform?
To start off, it is not possible to use Timer 0 reload values to vary the frequency by 200 steps between 9 kHz and 12 kHz since it is a 8-bit timer and cannot provide that level of resolution. The D flip-flop can be used to create a one-bit counter which can be output to a pin. This can in-turn be used to run the PCA through ECI. Timer 2 can be used with the CLU to generate the 9 kHz frequency pulse. The reload value of this timer can be changed to change the frequency.
The CLU can be programmed in the Configurator to generate a 9 kHz bit counter.
This setting would result in a D flip-flop as shown below -
The PCA settings should be changed to use the ECI for PWM generation
Now, the duty cycle can be altered by changing the capture compare value of the PCA channel. The only constraint is that one GPIO pin should be available (depending on the CLU output) for the PWM counter to work. The code example attached shows how CLU, PCA+ECI can be used to generate PWM signals. By adding a push button, the user can change the frequency by changing the reload value of Timer 2.
What is the minimum code size for the EFM8 capacitive sensing library (cslib)?
The minimum code size for cslib is approximately 4 kB with the UART Profiler Output disabled. The UART Profiler Output is typically only used during development and can be removed in the release build of a project. Devices with 8 kB flash are recommended for applications using cslib.
How to use EFM8LB1/EFM8BB3 I2C slave, it looks quite different from SMBus peripheral.
The EFM8LB1/BB3 contains a I2C slave peripheral, it includes many interesting features which helps on high speed transfer but may cause confusion to the user who was familiar with legacy SMBus operation. Here we make a brief intro of I2C slave, and attach an I2C slave bootloader example code for reference. This code example has been written for EFM8BB3 but can be easily ported to EFM8LB1 if needed.
The I2C peripheral contains 2 bytes FIFO and 1 byte shift register for TX/RX individually. The I2C slave support auto ACK/NACK an I2C master, it is controlled by BUSY bit field of I2C0CN0 register. In default, the BUSY is "1" which the device will not respond to an I2C master. All I2C data sent to the device will be NACKed. We should set this BUSY bit as "0", the device will acknowledge an I2C master. For a case, the master keep sending data to device, the device ACK the master automatically for max 3 ACKs since two bytes in FIFO and 1 byte in shift register. And then the SCL is hold low to indicate device is not capable to receive more data. We should check RXE bit field of I2C0FCN1 register to know if there is data in FIFO, read received data from I2C0DIN register.
The auto ACK feature makes difficulty on flow control, as we mentioned above, the SCL is hold low when the RX FIFO is full, so that device can handle the data. What about the master changes read/write direction? There is another feature can helps on this situation. The FACS bit field of I2C0ADM register. The defaults value is "1" which means FORCE_STRETCH. When this bit is set, clock stretching always occurs after an ACK of the address byte until firmware clears I2C0INT bit. With this clock stretching feature, we are able to hand the flow control during read/write direction changes.
There is an I2C slave bootloader example code which base on AN945, please take a look into it and have a reference on how the I2C slave state machine works. The I2CSlave state machine is described in two Flow Diagrams in the Reference Manual (Fig 17.7 and Fig 17.8) and can be condensed down to this Status Decoding table (Table 17.1 in the Reference Manual - https://www.silabs.com/documents/public/reference-manuals/efm8bb3-rm.pdf)
The I2C Bootloader is designed to work just like the SMBus Bootloader which is described in detail in AN945 - https://www.silabs.com/documents/public/application-notes/an945-efm8-factory-bootloader-user-guide.pdf. The boot_I2C.c file in the attachment shows how the I2CSlave peripheral is being used - one may notice that only three states are defined in the code while the Table shown above describes a lot more. There are a couple of reasons why some states are not included in the Bootloader code -
Why does changing the PGA setting from, say, 8 to 32 increase the current consumption of the circuit?
The PGA on a SigmaDelta ADC like the one on C8051F353 is usually implemented with CMOS switched capacitors. Essentially, there is a capacitor of a certain size that is being switched in and out at a certain frequency. This creates a variable resistor that can be scaled with frequency or capacitor size, relative to another reference capacitor in the design. The variable resistor is how we adjust the gain of the PGA.
For certain gain settings, we scale the capacitor size and the for higher gain settings (over 8x), we adjust the frequency of the switched cap. The extra supply current is probably clock current going to those switched capacitors, and some from the switches themselves, being switched at a higher frequency.
After locking code space using the lock byte, I am unable to connect to my JTAG MCU (eg C8051F020, C8051F120) using the Flash Utility or IDE. Is this the expected behavior?
For MCUs with a JTAG interface, it is not possible to connect to the device using the Flash Utility or IDE after locking the code space. To restore debug access, the device must be erased (ie "erase code space" in the Flash Utility or IDE).
For MCUs with a C2 interface, it is possible to connect to the device using the Flash Utility or IDE after locking the code space, however, the flash can not be read. Attempting to read locked flash will result in 0x00.
What does "K" mean in the C8051F120-TB-K part number?
We recently updated the legacy kit naming convention. The C8051F120-TB is the board only and the C8051F120-TB-K is the kit which includes the C8051F120-TB plus the box with the quick start card.
The SMBus module of EFM8 devices can support master, slave, and multi-master modes. When SMBus operating as a master, the SMBus clock source can be selected by SMBCS bit field, it can be Timer 0/1 Overflow or Timer 2 High/Low Byte Overflow.
The overflows from the selected clock source will determine both the bit rate and the absolute minimum SCL low and high times. The device will hold the SCL line low for 1 overflow period, and release it for 2 overflow periods. The THIGH is typically twice as large as TLOW, of course, the actual SCL output may vary due to other devices on the bus.
So the selected clock source should typically be configured to overflow at 3 times the desired bit rate, for example, if desire 100K SMBus bit rate, the overflow rate of the selected clock source should be 300KHz. The figure below illustrate how to generate the SCL by the timer source overflows.
For example, select the Timer 1 overflow as the SMBus clock source, configure the Timer 1 as 8-bit Counter/Timer with Auto-Reload (mode 2), and select the timer 1 clock source as system clock divided by 4.
The overflow rate of Timer 1 in 8-bit auto-reload mode is below.
If set the TH1 with 0xEC, the Ftimer1 will be around 300KHz with 24.5MHz system clock divided by 4.
The finial SMBus bit rate will be Ftimer/3, around 102Kbps.
To register a license for Keil C51, two components are needed - a CID (Computer ID) and PSN (Product Serial #). The CID is different from computer to computer, so you cannot simply copy the license information from one computer to another.
If a computer cannot access the Internet, we can obtain its PSN/CID and register it with another computer that can access the Internet. The CID and PSN can be obtained in one of the following ways:
With both the PSN and CID, register for a license here: https://www.keil.com/license/install.htm. The license (LIC) can be installed under Studio, back in the Licensing Helper ([Help] > [Licensing] > [Keil 8051 ...]), or in Keil uVision under [File] > [License Management].