How can I generate a periodic signal using the DAC?
To generate a periodic signal on the DAC, the DAC should be configured to update on a Timer overflow. The timer overflow can be used to define the sampling rate or time steps between changes in output level. The associated timer can be used as an interrupt source to interrupt the processor when a new DAC value needs to be written to the DAC registers. Application Note AN123 shows some examples of using the C8051F02x family DACs as function generators.
When using the PCA in 8-bit or 16-bit PWM mode, how can I obtain a duty cycle of 0%?
A 0% duty cycle signal can be generated by clearing the ECOMn bit in the PCA0CPMn SFR. The resulting output signal will be continuously low. Remember to set the ECOMn bit back to a 1 to resume normal PWM operation.
Can the Current-Mode DAC be used to generate rail-to-rail Voltages?
No. To perform to datasheet specifications, the output voltage of the current-mode DAC must remain within the Output Compliance Range for the DAC. The specification for the output compliance range can be found in the IDAC Electrical Characteristics table in the datasheet.
When using an external resistor to generate an output voltage, the resistor value should be chosen such that the maximum output voltage remains within the output compliance range at the maximum desired output current.
What are the benefits of a double-buffered Enhanced SPI?
Both the receiver and transmitter of the Enhanced SPI peripheral are double-buffered. The benefit of having a double-buffered transmiter is that the next byte can be written to the SPI data register while data is being transmitted. The Transmit Buffer Empty TXBMT bit in the SPI0 Control Register SPI0CN should be tested before writing the next byte to the SPI data register.
The Receiver is double-buffered on all C8051 devices with an SPI and allows a byte to be read from the SPI0DAT register while new data is being shifted into the shift register.
I want to generate a Voltage using the IDAC. Can I just use a resistor?
Yes, just a resistor is usually sufficient to output a voltage using the Current Mode DAC. For example, for a 10-bit IDAC, with values between 0x000 and 0x3FF:
In the above diagram, if a load resistance (placed across the "VCOMP to GND" port) is much smaller than R, then the voltage across R will be (at least partially) dependent on the load resistance. This is due to non-negligible flow of current through the load when the load resistance is comparable to or smaller than R. In such cases, an opamp voltage follower (buffer) should be used after the resistor to ensure correct voltages (isolating the voltage conversion of IDAC output from the load).
Selecting the resistor value:
Pick 'R' such that the fullscale output current (IFULLSCALE) from the IDAC results in a voltage that satisfies the Output Compliance Range (VCOMP) of the IDAC.
RMAX = VCOMP / IFULLSCALE
The Output Compliance Range limits the maximum voltage at the IDAC output. Refer to table 'IDAC Electrical Characteristics' in the relevant datasheet for more information and details.
The fullscale current of the IDAC is set to a certain value by default upon reset, but this value may be changed as needed. For example, with the C8051F33x devices, the fullscale current is 2 mA by default, but may be changed to 1 mA or 0.5 mA by modifying the IDA0CN SFR.
It is technically possible to use the SMBus peripheral in polled mode. However, the SMBus peripheral was designed to be used as an interrupt-driven peripheral, and using the SMBus as a polled peripheral is likely to cause violations of the SMBus timing specifications. For this reason, Silicon Laboratories does not provide code examples for using the SMBus peripheral in polled mode.
It is strongly recommended that all SMBus communications be handled in an SMBus interrupt service routine. Please see the Application Notes below for examples of how to write a SMBus interrupt service routine.
I have a USB interface in my system, and I think there may be a hardware problem. Can you suggest any generic hardware troubleshooting tips?
Here are a few USB hardware troubleshooting tips for USB systems:
On connecting to the computer, if the device manager says that its an unknown device even if you have the correct drivers installed, it is possible that the data lines are switched. The pinout for a USB-B receptacle can be found on Page 94 of the USB 2.0 specification sheet. The latest revisions and errata are available at http://www.usb.org/.
USB cables are specified to have the following color coding internally:
Pin1 = VBUS = Red
Pin2 = D- = White
Pin3 = D+ = Green
Pin4 = GND = Black
If you have a PCB without soldermask with traces on the top layer, the USB-B receptacle's shield/chasis might be shorting out one or more of the signals.
The USB receptacle on the C8051F320TB target Board is the USB-B type (not USB mini-B).
Is it ok if I operate at supply voltages near the Absolute Maximum Ratings as long as the supply voltage never exceeds the maximum?
Device operation at or near the absolute maximum ratings is not specified. However, stresses beyond the absolute maximum rating will most likely result in permanent device failure. Exposure to absolute maximum ratings (or operating conditions near absolute maximum ratings) for extended periods may affect device reliablility.
Device operation is only specified for the operating range listed in the 'Electrical Charactaristics' table in the device datasheet.
My Voltage DAC output is always near 0V, regardless of what I write to the data registers. I have enabled the DAC using the control register. What could be happening?
A voltage reference is necessary for the Voltage DAC to operate. Make certain that you have selected a valid voltage reference for the DAC. Refer to the chapter 'Voltage Reference' in the datasheet for details about selecting the voltage reference for the DAC.
This could happen if you are using a 3-wire SPI by excluding NSS. Since NSS is not present, there is no synchronization between the master and the slave. During the power up of the master device, the SCK pin might switch a few times, which will be interpreted by the slave as the first clock and it will start shifting in the data. This creates an offset in the data stream, resulting in slave data being shifted by a constant 'n' bits.
To prevent this from happening, any of the following could be done:
Use of the NSS signal for synchroniztion (4-wire SPI)
Exchanging a pre-arranged data header before the actual data stream that can help the slave find out the shift in data. Once this shift is detected by the slave, it can switch off its SPI peripheral and restart to capture the data without any shifts.
Does the Weak Pull-Up Disable (WEAKPUD) bit disable the weak pull-ups on the /RST or JTAG lines?
The global weak pull-up disable bit only affects Port I/O pins. It does not disable the weak pull-ups which are present on the /RST or (where applicable) the JTAG lines. The weak pull-ups on the /RST and JTAG lines are always active when the device is powered on.
What are the various power configurations available for the Silicon Labs USB devices?
For CP210x power options, please follow the link in the 'Related Articles' section.
C8051F32x / C8051F34x
The various power connection options available for the C8051F32x and C8051F34x devices are:
USB Self-Powered, Regulator Disabled
No USB Connection
These are described with diagrams following the Section 'VBUS detection' of the datasheet in the 'Voltage Regulator' Chapter. It is not recommended to leave the REGIN input floating even if the regulator is turned off and the device is powered directly via VDD. In this case, it is safe to have VDD and REGIN tied together. The options are illustrated below:
I am using an external device on the /RST line which can drive both logic high and logic low states. I know that the /RST line on your device is capable of driving itself low at power-on and during other reset events. Will this be a problem?
For proper power-on reset and supply monitor reset behavior, the /RST line should not be directly driven to a logic high state with any low-impedance circuit. If circuitry connected to the /RST line is capable of driving it to a logic high state, it is recommended that a series resistor (between 400 and 1000 Ohms) be included to allow the reset circuitry to drive a logic low level at the /RST pin when necessary.
A 0% duty cycle can be achieved by clearing the ECOM bit for the PCA module generating the PWM waveform. For other duty cycles, the ECOM bit must be set to '1', and the PCA will generate the duty cycle according to the equations below:
Should the VDD monitor be enabled or disabled when writing to FLASH?
It is strongly recommended that the VDD monitor be enabled prior to any FLASH write operations from application code. This is to prevent any data corruption resulting from power irregularities or power-down conditions.
The VDD Monitor will cause a reset if the supply voltage falls below VRST; It should be enabled and selected as a reset source.
Note that there is a power-up time for the VDD monitor circuit after enabling it, within which it should not be selected as a reset source.
Refer to the table 'Reset Electrical Characteristics' in the datasheet for VRST and power-up time values.
For more details about the VDD Monitor, refer to datasheet section 'Power Fail Reset / VDD Monitor'
When using a PCA channel in an output mode (8 or 16-bit PWM, Frequency Output, High Speed Output), how can the pin be forced to a known logic state (high or low)?
The output may be set to a logic high output by writing 0x00 to the PCA module Capture/Compare mode SFR PCA0CPMn. When the PCA module is placed back into the desired mode, the output pin will remain high until a PCA event causes the pin to go low.
To set the output pin to a low state, it is necessary to allow the PCA to run through a condition that will cause the pin to toggle low. This is slightly different for each output mode of the PCA:
8-bit PWM Mode: In 8-bit PWM mode, the PCA module will toggle the output pin low whenever the low byte of the PCA counter (PCA0L) overflows from 0xFF to 0x00 (unless the module is set to 100% duty cycle). Clearing the ECOMn bit for the module to '0' produces a 0% duty cycle, starting at the next PCA0L overflow.
16-bit PWM Mode: In 16-bit PWM mode, the PCA module will toggle the output pin low whenever the full PCA counter (PCA0HCA0L) overflows from 0xFFFF to 0x0000 (unless the module is set to 100% duty cycle). Clearing the ECOMn bit for the module to '0' produces a 0% duty cycle, starting at the next PCA0HCA0L overflow.
High Speed Output Mode: In High Speed Output mode, to set the pin low (if the output is already high) it is necessary to schedule a match event. A match event occurs anytime the main PCA counter (PCA0HCA0L) increments and becomes identical to the PCA module's Capture/Compare register (PCA0CPHnCA0CPLn). Once the pin is low, clearing the ECOMn bit for the module will disable the match function so that the pin remains low. Clearing the TOGn bit will prevent the pin from toggling again, but the match function will still be active (this places the PCA module into Software Timer Mode). Clearing TOGn or ECOMn when the pin is high will allow the pin to remain high.
Frequency Output Mode: In frequency output mode, to set the pin low (if the output is already high) it is necessary to schedule a match event. A match event occurs anytime that the main PCA counter's Low byte (PCA0L) increments and becomes identical to the low byte of the PCA module's Capture/Compare register (PCA0CPLn). Once the pin is low, clearing the ECOMn bit for the module will disable the match function so that the pin remains low. Clearing ECOMn when the pin is high will allow the pin to remain high.
Can I use the C2D pin as a general purpose port I/O pin and for debugging at the same time?
Yes, the C2 Data pin (C2D) can be shared for general purpose I/O and debugging if the appropriate external connections are made. Application Note 'AN124-Pin Sharing Techniques for the C2 Interface' discusses this topic in detail and shows several examples of sharing the C2D pin between C2 traffic and general purpose I/O.
What could be the reason for getting a reset immediately after enabling the comparator?
If you enable Comparator0 as a reset source (C0RSEF=1 in RSTSRC SFR) immediately after powering on the comparator (CP0EN=1 in CPT0CN SFR), it might cause an unwanted reset. Please refer to the datasheet in the 'Comparator' chapter for the Power-up time listed in the 'Comparator Electrical Characteristics' table. This is the minimum time between enabling (powering-up) the comparator and allowing it to be a reset source.
Following a reset triggered by the comparator, the C0RSEF flag in the RSTSRC SFR will be set.
Please note that the comparator output is unpredictable if either of the comparator inputs is floating or if both of them are connected to the same voltage level.
The following table is often helpful to know when a reset could occur (after the above stable condition is reached):