Areas of the FLASH code space on a device appear to be modified or corrupted inadvertently.
Any system that contains routines which write or erase FLASH memory involves some risk that the FLASH write/erase routines will execute if the CPU is operating outside its defined operating range of VDD, temperature, or system clock frequency. The goal is to minimize this risk by enabling FLASH writes and erases as little as possible (only one place in code can write to FLASH; only one place in code can erase FLASH) and by ensuring that the CPU is always operating in a defined mode. The most common causes of FLASH corruption are 'software' based; that is, the CPU executes MOVX write operations while the PSWE bit is set to a '1'. This can happen if the CPU vectors to an interrupt service routine that performs an assignment to a variable located in xdata or pdata space. Some devices, like the C8051F3xx families, include a FLASH Lock and Key sequence (FLKEY) to help minimize this risk.
Many things can be done in the code to prevent FLASH corruption, such as explicitly enabling the VDD monitor (where applicable) and disabling interrupts whenever PSWE = 1. Fortunately, there are some additional protection mechanisms that can make the system even more robust.
The most likely candidate for potential FLASH corruption is the CPU exiting reset prematurely (before VDD reaches Vrst) on initial power-on. This is usually caused by a system VDD rise time that is slower than the 1 ms specification in the datasheet (for 'F30x, 'F31x, and 'F33x family devices). One way to address this is to install an off-chip VDD brownout circuit on the /RST pin. Another way is to implement additional safeguards in code to ensure that the on-chip VDD monitor is always enabled whenever a write or erase to FLASH memory is attempted. Of course, it is also perfectly acceptable to implement both of these (hardware and software) schemes.
One other potential system parameter that can affect CPU code execution reliability is the system clock source. If the system clock is derived from an external crystal oscillator, then external EMI coupling can cause a runt pulse to be coupled into the system clock net which can lead to indeterminate operation. One way to lessen this risk is to enable the 'divide by 2' option in the external crystal oscillator. Better ways are to use the internal oscillator or use an external CMOS can oscillator (one that is encased in a metallic shield to protect the sensitive crystal elements from external coupling effects).
Another potential clock source related problem can occur on devices which are operating at system clock speeds of greater than 25 MHz. If a device is specified to operate at greater than 25 MHz, make certain that the Flash Read Timing bits (FLRT) located in the Flash Scale (FLSCL) register are set properly for the speed of the clock. If the CPU is operating at speeds above 25 MHz and the FLRT bits are not set properly, incorrect operation can occur because opcodes can be read incorrectly from the code memory.
These recommendations are summarized below:
Hardware Check List:
1. Use a good power supply decoupling strategy (both large and small ceramic capacitors) that comprehends ESD if ESD is a threat to your product (exposed connectors, etc. This includes any USB system with a connector.). Add Transient Voltage Suppression diodes on the power supply net if ESD is a threat.
2. Stress-test the system by cycling power frequently on the production units.
3. Stress-test the software by running it on a modified target board (all decoupling capacitors removed) and using a function generator to supply VDD (1 Hz triangle wave test and narrow (<1 us) deep (1.5 V below nominal VDD) pulse train test).
4. Make certain that in addition to the VDD monitor, the Missing Clock Detector is enabled as a reset source.
5. If using an external crystal, make sure the crystal traces are short and are protected by ground plane. Protect the external oscillator circuit from physical disturbances. Note that in addition to layout, crystals are also sensitive to temperature.
6. If the system is operating in an electrically noisy environment (high levels of EMI due to large switching currents or voltages, such as relays, motor control applications, or RF transmitters), use an external 'can' oscillator if a precision time base is needed, or use the internal oscillator on the device. Do not use a crystal oscillator in these applications as electrical interference can cause the CPU to be exposed to 'runt' pulses that violate the minimum system clock period high and low times.
7. Switch to the internal oscillator during Flash write or erase operations. The external oscillator can continue running, and the CPU can switch back to it when the Flash operation has completed.
8. If unable to switch to the internal oscillator, use XTAL/2. This will minimize the chance that a runt pulse will be presented to the CPU.
9. If unable to switch to the internal oscillator, poll for XTLVLD prior to the Flash operation to confirm that the oscillator is running and is stable.
10. If unable to switch to the internal oscillator, use a crystal drive strength that is one value higher than normal during the Flash operation, if possible.
11. If operating at system clock frequencies above 25 MHz, make certain that the Flash Read Timing bits in FLSCL are set appropriately for the operating frequency.
Simple Software Checklist:
12. Have exactly one routine which writes Flash memory and one routine that erases Flash memory. These should be the only two places in code where the PSWE bit is set to a '1'.
13. Disable interrupts when PSWE = 1 inside Flash write and erase routines.
14. Disable interrupts using 'EA = 0; EA = 0;'.
15. Minimize number of instructions between 'PSWE = 1' and 'PSWE = 0'.
16. Perform any pointer address calculations or loop variable updates only while PSWE is '0'. Use a simple pointer dereference, for example '*pwrite = the_data;'. Do not couple an address update with the dereference, such as '*pwrite++ = the_data;'.
17. Explicitly locate Flash write pointers in 'data' or 'idata' segments, not 'pdata' or 'xdata'. Be cautious of using 'compact' and 'large' memory models as these models will store automatic variables, such as pointers and loop counters, in 'pdata' and 'xdata' segments.
18. If writing a series of Flash bytes, bracket the pointer dereference with PSWE writes as follows:
unsigned char xdata * idata pwrite;
unsigned char *source;
unsigned char mydata;
for (addr = 0; addr < 100; addr++)
// perform any pointer math or complex
// dereferencing when PSWE = '0'
mydata = *source++;
// assign pointer when PSWE = '0'
pwrite = (unsigned char xdata *) addr;
// PSWE = 1
PSCTL = 0x01;
// initiate byte write using a simple
// dereference (no address increment or decrement)
*pwrite = mydata;
// PSWE = '0'
PSCTL = 0x00;
19. Find all instances in the code of writes to the Reset Sources register (RSTSRC), and confirm in each one that the VDD monitor is being explicitly enabled as a reset source. In particular, check any instances where code is trying to force a Software Reset, as many programmers will inadvertently disable the VDD monitor when forcing a Software Reset.
20. Also confim that all writes to RSTSRC use a direct assignment operator (=), and do not use a bit-wise operator such as '|=' or '&='.
21. Enable the VDD monitor and enable it as a reset source inside Startup.A51 (for Keil C51), or inside _sdcc_external_startup() (for SDCC). If using a different compiler, check your compiler documentation for modifying system start up code.
22. On devices which have a VDM0CN register, remove any delays between enabling the VDD monitor and enabling the VDD monitor as a reset source.
23. Enable the VDD monitor and enable it as a reset source inside your Flash write and erase routines, before the Flash write or erase operation happens.
24. For bootloading schemes, transmit the Flash lock and key sequence (0xa5, 0xf1 to be written to FLKEY) across the bootloading interface. Do not place the key sequence in code space if you do not have to.
25. For non bootloading schemes, derive the Flash lock and key sequence using an algorithm (such as XOR with 0x55), such that if program control enters the Flash write or erase routine by accident, an incorrect Flash key sequence will be delivered to the hardware, thus protecting the Flash memory.
26. For schemes in which Flash write/erase operations will not be needed until the next system reset, intentionally write an incorrect Flash Lock and Key sequence to FLKEY. This will cause the hardware to ignore any further write or erase attempts.
27. Perform address bounds checking inside the Flash write and erase routines. Generate a system reset if the target address is out of bounds (make sure that you do not accidentally disable the VDD monitor as a reset source).
Advanced Software Checklist:
28. Using the linker (or compiler if it can do it), explicitly locate the Flash write and erase routines near the end of code space. This will help prevent them being accidentally executed due to a branch failure immediately above their entry point.
29. Place 'trap' functions immediately before the Flash write and erase function entry points, such that if program control is 'falling through' a previous routine, it will hit the trap instead of the Flash write/erase function. The trap routine should force a system reset.
Application Note AN201 is a resource for Flash modification code examples. Application Note AN201 - 'Writing to FLASH from Firmware' can be found at the following URL:
Some of the Silicon Labs devices use a JTAG debugging port, but do not support Boundary Scan. Can I still use these in a JTAG boundary scan chain?
JTAG Boundary Scan is not available on certain microcontroller device families. However, these devices can still participate as part of a JTAG Boundary Scan chain in BYPASS mode. These devices can also participate in a JTAG Daisy Chain for debugging and downloading firmware.
BSDL files are available for these devices by contacting us through our web support form:
BSDL files for all other JTAG devices are found at the following link:
What should I do with unused I/O pins?
Unused pins which are not connected to anything external to the device may be left as open-drain, high-impedance (tri-state) inputs, or configured to drive low or high in push-pull mode.
If an unused pin is configured as an open-drain input, connected to ground externally, and the weak pull-up for that pin is enabled, there will be some current flow due to the weak pull-up on the device. In low-power applications, this is generally not desirable. If an unused port pin must be connected to ground externally in a low power application, it is recommended that the weak pull-up for the pin be disabled. On devices where the pin can also function as an analog input, placing the pin in analog input mode will disable the weak pull-up. If the pin is not capable of being configured in analog mode, the weak pull-ups can be disabled. On some devices like the SiM3U1xx, these weak pull-ups can be disabled on a port-by-port basis. On devices that do not support this feature, the weak pull-ups are disabled globally for the entire device.
How do I measure a signal whose amplitude is higher than the device's voltage supply (VDD and/or AV+)?
Analog input pins must not be exposed to voltages outside of those specified in the device's Absolute Maximum Ratings table in the datasheet. Furthermore, the ADC will not be able to produce a unique output code for voltages that are below ground voltage or above the voltage reference (VREF) voltage. For a differential measurement, the difference between the two input voltages cannot be greater than the VREF voltage.
NOTE: Even in differential mode, the ADC input signals must not exceed the ratings in the datasheet. For example, voltages below the device's ground potential can damage the device, even when making differential measurements.
If the signal to be measured is outside of these voltage ranges, an external circuit must be used to condition the amplitude and DC offset (or bias) for proper measurement. This is most easily accomplished with an op-amp circuit, such as an inverting amplifier, as shown below. Using this method, the amplitude and bias of the signal can be changed with high input impedance and low output impedance. Furthermore, this circuit can also be designed as a low-pass filter to meet the anti-aliasing requirements of the design.
How many clock cycles will occur between an interrupt event and the servicing of the interrupt?
Before the processor core vectors to the ISR when an interrupt is posted, it will execute one instruction. Depending on when in the instruction the interrupt occurs, and what the actual instruction is, the core will vector to its ISR at different times. The detection of the interrupt and the vectoring to the interrupt vector table take 5 SYSCLK cycles. Also, if the Interrupt Serivice Routine is not located in the Interrupt Vector Table, then an additional LJMP (or AJMP) to the ISR entry point will add another 4 (or 3) SYSCLK cycles of latency. The compiler might also determine that foreground register values need to be preserved, and these values will be saved by pushing them onto the stack.
I would like to use the CIP-51 MCU's STOP Mode to save power. How do I recover from or 'wake' from STOP Mode?
The CIP-51 MCU STOP Mode offers a very low current state in which the controller shuts off its oscillator. However, the CIP-51 MCU requires a RESET in order to recover or 'wake' from STOP Mode. This means that the CIP-51 will have to reinitialize all of its peripherals to resume operation (code execution will begin at code address 0).
Waking from STOP mode requires that an external event (or signal) be applied to the device to cause a reset. This can be accomplished via a power-on reset or forcing a reset signal at the reset (/RST) pin. This is not always practical, so Silicon Laboratories CIP-51 MCU's allow an on-chip voltage comparator to be configured as a reset source.
To do so, please see the 'Reset Sources' section of the datasheet for configuring the comparator as a reset source, and the 'Comparators' section of the datasheet for information concerning the configuration of a comparator. Keep in mind that often, external components will be added (typically resistors) to bias the comparator properly such that the external signal will trigger a reset.
NOTE: There is a 'Power-up Time' associated with comparators once enabled. Do not set the comparator as a reset source until the power-up time has elapsed after enabling the comparator, or a false reset signal may occur, as comparator output is indeterminate during power-up. Power-up time is posted in the comparator's electrical characteristics table found in the Comparator section of the datasheets.
I am using SMBus/I2C communications. What is Bus Free Timeout? What is SCL Low Timeout?
Bus Free Timeout
On C8051Fxxx devices when the appropriate bit is set, the bus is considered 'free' (not in use) if the SCL and SDA lines are high for 10 SMBus clock periods. When the bus is free, an SMBus master with a transfer pending can take over the bus and generate a start condition to start a new transfer.
SCL Low Timeout
SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period, in order to have additional time to respond to a 'fast' master.
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than 25 ms as a timeout condition. This is called SCL Low Timeout.
Devices that have detected the timeout condition must reset the communication no later than 10 ms after detecting the timeout condition, so that the bus can recover.
How many interrupt priority levels are available on the CIP-51 microcontroller?
There are two interrupt priority levels: HIGH and LOW.
A HIGH priority interrupt may in turn interrupt (or preempt) a LOW priority interrupt. If this happens, the CIP-51 will return to the original LOW priority interrupt upon completion of servicing the HIGH priority interrupt (i.e., by executing the RETI instruction).
NOTE: Interrupts assigned the same priority level cannot preempt each other. A second, same-priority interrupt will be treated as a pending interrupt, and be serviced upon return from the first interrupt. HIGH priority interrupts will never be preempted by another interrupt.
Interrupt priorities are documented in the 'CIP-51 Microcontroller' section of each devices' family datasheet.
How should I configure the external oscillator pins in my firmware if I am using an external oscillator source?
On devices with dedicated oscillator pins (such as the C8051F12x family), the pins will automatically configure for the selected external oscillator mode.
For devices on which the external oscillator pins are shared with GPIO pins (such as the C8051F30x family), the GPIO pins associated with the oscillator must be configured as described below:
1. For an external crystal oscillator, both port pins XTAL1 and XTAL2 should be configured as analog inputs.
2. For 'RC' mode or 'C' mode, XTAL2 or EXTCLK should be configured as an analog input.
3. For CMOS clock mode, XTAL2 or EXTCLK should be configured as a digital input.
Whenever an external oscillator option is used on a device which has the oscillator pins shared with GPIO, the associated crossbar should be configured to skip the pins used by the oscillator circuit to avoid any conflicts with crossbar peripherals.
What are the max/min voltages on any pin?
The max/min voltages on any pin are listed in the 'Absolute Maximum Ratings' table in the device datasheet. Voltages beyond the limits listed in this section may cause permanent damage to the device. Exposure to maximum rating conditions for extended periods may affect device reliability.
What is the minimum digital supply voltage (VDD) for which the data in the RAM will be retained without any corruption?
The minimum RAM retention voltage varies for each device family. The device datasheet should have the minimum RAM retention voltage listed in the 'Global Electrical Characteristics' table.
My ADC output is always reading full-scale. What could be wrong?
Some of the reasons you could be getting continuous full-scale outputs from the ADC and respective solutions:
1. The voltage you are trying to measure is greater than VREF.
If input voltage is greater than VREF, output will be saturated; You could consider scaling down the input signal swing using an external circuit or increasing VREF. In case of increasing VREF, please keep in mind the 'Absolute Maximum Ratings' of the analog voltages that can be applied to port pins and also the ADC input voltage range. Please refer to the 'Absolute Maximum Ratings' section and the ADC section of the datasheet for specifications.
Some devices include programmable gain amplifiers (PGA) used to amplify the input signal. Verify that the gain setting for the PGA is not causing the input signal to exceed the VREF voltage.
2. The VREF Control Register has not been configured correctly.
Select the correct VREF you want to use -- Internal/External. If you are using an external VREF and if the VREF pin is a shared I/O pin in your device, please make sure that the pin is configured as analog input and skipped by the Digital Crossbar .
It is usually helpful to measure the voltage across the VREF pin and ground to check the actual VREF being applied. You could also measure the input voltage with respect to ground to compare.
I am generating a PWM signal using the PCA. How do I change the PWM waveform frequency?
The PWM frequency is dictated by the rate of the PCA counter/timer overflow. The overflow rate is determined by the number of bits in the PCA timer (8- or 16-bits) and the time base input to the PCA timer. For this reason, the only way an N-bit PWM waveform frequency can be changed is to change the time base input to the PCA timer.
For example, you could change the configuration of the PCA to increase the input from SYSCLK/12 to SYSCLK/4. Alternatively, you could also increase the system clock frequency of the 8051. However, this is not typically practical.
If it is critical to have control over the PWM frequency, consider using High-Speed Output Mode. This allows the designer to schedule waveform transitions to produce waveforms of specific duty-cycle and frequencies. However, this PCA mode requires some software intervention (typically an interrupt service routine). This technique is detailed in Application Note, 'AN107 - Implementing 16-Bit PWM Using the PCA'. AN107 not only illustrates using High-Speed Output Mode to produce a 16-bit PWM output, but shows how to produce any N-bit PWM waveform.
PWM Code examples for other device families with the PCA peripheral are installed with the IDE and by default are located at the following location:
The Silicon Laboratories IDE can be downloaded from the IDE download page: http://www.silabs.com/products/mcu/Pages/SiliconLaboratoriesIDE.aspx
Application notes can be downloaded from the Silicon Laboratories MCU applications web page: https://www.silabs.com/products/mcu/Pages/ApplicationNotes.aspx
According to my calculations, the minimum tracking time plus the conversion time using the maximum SAR clock speed is faster than the maximum sampling rate. Does this mean I can sample faster than the maximum sampling rate listed in the datasheet?
Although the ADC may be capable of operating slightly faster than the maximum speed listed in the datasheet, it is not recommended. The ADC is not guaranteed to function or meet datasheet specifications when it is operated beyond any of the datasheet limits.
There are a number of reasons why an 8051 interrupt which is posted cannot be serviced:
1) The interrupt is not enabled in the IE or EIE1, EIE2, etc. register.
2) Global interrupts are not enabled (the EA bit is not set to '1').
3) The interrupt is set to LOW priority, and another interrupt is being serviced.
4) The interrupt is set to HIGH priority, and another HIGH priority interrupt is being serviced.
Note that an interrupt is not finished being 'serviced' until a RETI instruction is executed.
Additional debugging tips:
1) Make certain that all enabled interrupts have a corresponding Interrupt Service Routine (ISR).
2) Make certain that the appropriate interrupt-pending flags are cleared before exiting an ISR.
3) Check that the appropriate interrupt number or vector location is being serviced by the ISR. The interrupt numbers and vector locations can be found in the CIP51 chapter of the product datasheet.
My DAC output appears to be missing codes. I write to the Low byte but the Output doesn't change. Why?
In 'Update on Demand' mode, which is the only update mode on C8051F000/1/2/3/5/6/7 and C8051F010,11,12,15,16,17 devices, writes to the DAC Low byte (DAC0L) are latched and held until the DAC High byte (DAC0H) is written. The DAC0 output actually takes effect after the write to DAC0H. Thus it is important in software to write the Low byte first.
Note that some compilers which support a 16-bit SFR data type such as 'sfr16' may write the High byte of the SFR address before the Low byte. See your compiler documentation for additional details on the 'sfr16' feature. Note that if the DAC is configured for 'Update on Timer Overflow', the order in which the High byte and the Low Byte are written is not important.
Why can't I set a breakpoint at a line of code? I'm getting a 'No address correlation for Line #' error message.
The IDE will only allow a breakpoint to be set if it is able to resolve a Program Counter address that corresponds to the target line of source code. The IDE will report the 'No address correlation for Line #' error if:
To determine if the line of code has been optimized out, try single-stepping through the code prior to and including the source line of interest with the Disassembly window open. The Disassembly window in conjunction with the Program Counter indicator will allow a better view into the program flow.
What size loading capacitors do you recommend for XTAL1 and XTAL2 when using the external oscillator in crystal mode?
The recommended load capacitance (CL) for a given crystal is generally specified in the crystal manufacturer's datasheet. The specified load capacitance is the total load capacitance which should be used for that crystal (as opposed to the capacitance needed at each leg of the crystal). For example, if Ca is the capacitor for one leg of the crystal, Cb is the capacitor for the other leg of the crystal, and Cs is the stray capacitance of the PCB, the load capacitance can be calculated with the following equation:
CL = ((Ca * Cb) / (Ca + Cb)) + Cs
Cs for a typical PCB is about 2 pF to 5 pF.