How does a SAR converter work, and what do all the different options mean?
Answer
SAR is an abbreviation for Successive Approximation Register. This is a particular type of Analog to Digital converter.
A SAR ADC uses a series of comparisons to determine each bit of the converted result. Therefore, a SAR ADC needs at least n+1 clock cycles to convert an analog input to the ADC to a result, where n is the number of bits of the ADC.
How it Works
The analog input is tracked by the SAR ADC, then sampled and held during the conversion. The sampled input is compared to the value of an internal DAC, which adjusts in binary increments and attempts to get as close as possible to the sampled value.
In the example below, VREF = 2.4 V and the analog input to the SAR ADC (4 bits for this example) is 0.7 V:
Step 1: First the SAR ADC tracks the analog input value. Each SAR ADC will have a minimum tracking time.
Step 2: The analog input is sampled and held during the conversion process.
Step 3: The DAC is set to half the full-scale output and compared to the held input value
Step 4: The result from the first comparison is moved to the test value, the next bit is set to 1, and the DAC output is compared to the input again. This step is repeated for each bit in the ADC:
... and so on.
Step 5: The final 4-bit result is posted and the ADC returns to tracking the input signal (Step 1).
Voltage Reference
All SAR ADCs require a voltage reference for the internal DAC to operate properly. The reference voltage determines the full-scale input and will affect the transfer function of the ADC.
¨
¨Note: On Silicon Labs MCUs, the voltage reference may be selectable between an External VREF Source, the Internal VREF, and the Supply Voltage.
SAR Clock
The SAR clock is used to time the internal SAR loop and determines the conversion time, but not the sampling rate. Sampling rate is the sum of the tracking time and the conversion time. The SAR clock should be selected to be as close to the datasheet maximum as possible without going over. The ADC is designed to work correctly at this speed and the conversion time will be faster, so the power consumption of the ADC will be lower. Furthermore, the rest of the time not used to convert a result can be used for tracking.
Please see the article in the 'Related Articles' section for more information.
How to Start a Conversion
On Silicon Labs microcontrollers, conversions can be initiated from three primary sources:
A write to the conversion-start bit (ADBUSY): This is otherwise known as 'polled-mode' or 'on-demand' mode, as conversions will occur whenever they're needed. This is useful for DC inputs that need occasional sampling. An example would be a 'System Monitor' application sampling temperature or supply voltage. If this type of sampling is used with AC inputs, there can be small amounts of sampling jitter due to instruction timing.
On-chip timer overflows: The on-chip timers provide a precise and periodic conversion start signal, which is useful for AC signals or in an interrupt-driven system.
The external conversion-start input (CNVSTR): The external input allows for sampling asynchronous to the microcontroller's internal system clock. This type of conversion-start signal can be used when sampling must be synchronized to an external event.
Other Considerations
Input Voltage
The absolute voltage at any analog input pin must be within the supply rails (AGND – 0.3V to AV+ + 0.3V) to avoid damage to the device.
The analog input voltage must be within the measurable input range for the ADC settings: Single-ended, Gain = 1: VREF > AIN+ > 0 V
Differential, Gain = 1: VREF > (AIN+ - AIN-) > -VREF
Multi-mode I/O pins can tolerate up to 5.8 V on the inputs, but analog signals must be less than or equal to the upper supply rail (AV+ or VDD) for proper measurement.
Input Protection
The common sources of over-voltage or under-voltage conditions include:
· Electro-Static Discharge (ESD)
· Amplifiers operating from separate supplies
· Hot-swapping board connections (connecting or disconnecting while the board is still powered)
Analog inputs can be protected from over- and under-voltage conditions using clamping diodes or current-limiting resistors, as shown below:
Please see the article in the 'Related Articles' section for more information.
Input Settling Time
The input to the SAR ADC “looks like” a single-pole RC filter. Each sample must have adequate time in the Tracking phase to allow enough settling time on the Sampling Capacitor:
The required settling time (in seconds) for a given level of accuracy is given by the following equation:
ln (2n / SA) * (RMUX + RSOURCE) * CSAMPLE
where:
n = ADC Resolution in Bits
SA = Settling Accuracy (% of one LSB)
Settling time can be maximized by:
· Using “Normal” tracking mode so the ADC is tracking whenever it's not converting.
· Increasing the time between successive conversions.
It is also important to change the multiplexer and PGA settings (if needed) to allow for the maximum settling time. The best time to modify the ADC multiplexer and PGA settings is during a conversion when the sampling capacitor is disconnected from the analog input, but it is also acceptable to change these settings while the ADC is tracking if there is enough time before the conversion begins. The worst case occurs when the multiplexer and PGA settings are changed right before a conversion is initiated.
Application Note AN119 'Calculating Settling Time for Switched Capacitor ADCs' has more information on settling time. Application notes can be found on the Silicon Laboratories Applications webpage: https://www.silabs.com/products/mcu/Pages/ApplicationNotes.aspx.
Single-Ended versus Differential
Single-Ended measurements are where the analog ADC input is measured with respect to ground. Single-ended measurements use a single external pin (AIN+)so that:
ADC Input = AIN+ - AGND
With single-ended measurements, the maximum input is VREF (so ADC Input = (AIN+ - AGND) = VREF) and the minimum input is 0 V (so ADC Input = (AIN+ - AGND) = 0 V). The C8051Fxxx SAR ADCs in single-ended mode use unipolar output with unsigned binary notation (so the maximum value for a 12-bit ADC in single-ended mode is 0x0FFF).
Differential measurements are where two inputs are measured with respect to each other. These types of measurements use two external pins (AIN+ and AIN-)so that:
ADC Input = AIN+ - AIN-
With differential measurements, the maximum difference between the inputs is VREF (so that ADC Input = (AIN+ - AIN-) = VREF) and the minimum difference between the inputs is -VREF (so that ADC Input = (AIN+ - AIN-) = -VREF). The C8051Fxxx SAR ADCs in differential mode use bipolar output in two's complement binary notation (so the maximum value for a 12-bit ADC in differential mode is 0x07FF).
For example, if AIN+ = 1 V and AIN- = 2V, the differential measurement is -1 V.
Miscellaneous C8051Fxxx SAR ADC Features
Window Comparator
The Window Comparator is a unique feature available on most of the Silicon Laboratories microcontroller devices. The Window Comparator automatically monitors the ADC output without CPU intervention and generates an interrupt only when the ADC output falls inside or outside a specified range (set by using the Window Comparator 'greater-than' or 'less-than' registers). This interrupt is a separate interrupt source from the other ADC interrupts and can be used in conjuction with the normal ADC interrupts or as a polled flag.
In the following example, the 'less-than' register is set to a higher value than the 'greater-than' register. In this case, the interrupt will be generated (if enabled) when the input is between the two values (less than the 'less-than' register but greater than the 'greater-than' register).
In the next example, the 'greater-than' register is set to a higher value than the 'less-than' register, so an interrupt will be generated (if enabled) when the ADC input is above the 'greater-than' threshold or below the 'less-than' threshold.
Programmable Gain Amplifier (PGA)
Many of the C8051Fxxx microcontrollers include a programmable gain amplifier in the ADC. This PGA can be used to increase the dynamic range on low-amplitude inputs. The PGA is implemented by scaling the SAR DAC output so that a signal of ½ VREF into the DAC results in a 2x gain on the input signal. This allows the PGA to improve the gain without changing the effective input impedance.
The higher gain ranges in the PGA produce more output noise, but techniques like oversampling and averaging can help reduce the noise. Application Note AN118 'Improving ADC Resolution by Oversampling and Averaging' contains more information on using these techniques. Application notes can be found on the Silicon Laboratories Applications webpage: https://www.silabs.com/products/mcu/Pages/ApplicationNotes.aspx.
High-Voltage Difference Amplifier (HVDA)
Some C8051Fxxx devices, like the C8051F040, also feature the High-Voltage Difference Amplifier (HVDA). The HVDA inputs can tolerate +/- 60 V and can be used to measure fully differential signals up to +/- 30 V. The HVDA has programmable settings that allow for the attenuation or gain of the input signal. The HVDA can be used to measure high differential voltages, reject high common-mode voltages up to +/- 60 V, and condition the signal voltage range to be suitable for input to the SAR ADC. The HVDA should be used with the ADC in differential mode for optimal performance.
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Direct-Memory Access (DMA)
Some C8051Fxxx devices, like the C8051F060, include a Direct-Memory Access (DMA) peripheral. With the DMA, the ADC conversion results can be sent directly into XDATA space without firmware intervention. The DMA does not initiate conversions; instead, it simply collects and stores the ADC output as directed.
The DMA can be programmed to accept conversion output from multiple ADCs in any sequence. The DMA is controlled through a series of pre-programmed instructions to minimize CPU usage and automatically repeats the instructions for single conversions or pre-programmed conversion sequences any number of times. In effect, the DMA can be given a programmable 'state machine' for collecting samples. The DMA also has flexible interrupt scheduling.
Common C8051Fxxx SAR ADC Questions
Q:I always see 0x0FFF at the output of my 12-bit ADC. What is the problem? A: There are several reasons why this might occur. The ADC may be in single-ended mode, and the input voltage to the ADC is too high. Another possibility is the voltage reference to the ADC is not properly configured.
Q:If the ADC input is limited to AV+, then what is the 0.5x PGA gain range for? A: While not providing measurement beyond the supply rails, the 0.5x gain range does allow for the measurement of signals above VREF. The 0.5x gain range can also be useful if the voltage reference used is less than ½ of AV+.
Q:When adding up the minimum tracking time and the minimum conversion time, it appears that the ADC can actually go a bit faster than your specification. Can it? A: The ADC is capable of operating at slightly higher speeds. However, the ADC parameters are tested and specified at the maximum sample rate listed in the datasheet, and specifications cannot be guaranteed at higher sampling rates.
Q:Can I apply 5 V to the ADC input? A: In most cases, no. The current exceptions to this rule are the HVDA inputs and the multi-mode pins on some devices. On multi-mode pins, the ADC will only measure accurately if the voltage on the analog inputs is within the supply rails. Applying voltages beyond the supply rails on analog-only input pins is a common cause of CMOS latch-up. Clamping diodes and current-limiting resistors can be used to help prevent over-voltage conditions.
Q:I am applying 2.1 V to the ADC input, but the code I get back from the ADC corresponds to 2.0 V. Why? A: One explanation is that variations in the reference voltage will cause variations in the transfer function of the ADC. In this case, the voltage reference may be higher than expected. Another possible cause is the ADC may have some offset and/or gain error. Check the appropriate datasheet to see whether the measured error is within the specified limits. Alternatively, the SAR clock for the ADC may be too fast, which is causing problems with the SAR DAC settling time.
Q:When I change the ADC MUX channel, I do not get the correct results from the ADC. It appears that the channels are interfering with one another. Why? A: This is likely to be the result of inadequate tracking or settling time for the conversion. Make certain that the MUX switching occurs at the best possible time (during a conversion when the sampling capacitor is disconnected from the analog input). Depending on the source impedance of the signals, it may also be necessary to slow down the sample rate or buffer the input signals. In some cases, poor layout techniques can lead to capacitive AC coupling, or 'crosstalk' between ADC inputs. To prevent this from occurring, try to keep the sensitive signals from running parallel to one another on the PCB.
SAR: Successive Approximation Register
Question
How does a SAR converter work, and what do all the different options mean?
Answer
SAR is an abbreviation for Successive Approximation Register. This is a particular type of Analog to Digital converter.
A SAR ADC uses a series of comparisons to determine each bit of the converted result. Therefore, a SAR ADC needs at least n+1 clock cycles to convert an analog input to the ADC to a result, where n is the number of bits of the ADC.
How it Works
The analog input is tracked by the SAR ADC, then sampled and held during the conversion. The sampled input is compared to the value of an internal DAC, which adjusts in binary increments and attempts to get as close as possible to the sampled value.
In the example below, VREF = 2.4 V and the analog input to the SAR ADC (4 bits for this example) is 0.7 V:
Step 1: First the SAR ADC tracks the analog input value. Each SAR ADC will have a minimum tracking time.
Step 2: The analog input is sampled and held during the conversion process.
Step 3: The DAC is set to half the full-scale output and compared to the held input value
Step 4: The result from the first comparison is moved to the test value, the next bit is set to 1, and the DAC output is compared to the input again. This step is repeated for each bit in the ADC:
... and so on.
Step 5: The final 4-bit result is posted and the ADC returns to tracking the input signal (Step 1).
Voltage Reference
All SAR ADCs require a voltage reference for the internal DAC to operate properly. The reference voltage determines the full-scale input and will affect the transfer function of the ADC.
SAR Clock
The SAR clock is used to time the internal SAR loop and determines the conversion time, but not the sampling rate. Sampling rate is the sum of the tracking time and the conversion time. The SAR clock should be selected to be as close to the datasheet maximum as possible without going over. The ADC is designed to work correctly at this speed and the conversion time will be faster, so the power consumption of the ADC will be lower. Furthermore, the rest of the time not used to convert a result can be used for tracking.
Please see the article in the 'Related Articles' section for more information.
How to Start a Conversion
On Silicon Labs microcontrollers, conversions can be initiated from three primary sources:
The external conversion-start input (CNVSTR): The external input allows for sampling asynchronous to the microcontroller's internal system clock. This type of conversion-start signal can be used when sampling must be synchronized to an external event.
Other Considerations
Input Voltage
The absolute voltage at any analog input pin must be within the supply rails (AGND – 0.3V to AV+ + 0.3V) to avoid damage to the device.
The analog input voltage must be within the measurable input range for the ADC settings:
Single-ended, Gain = 1: VREF > AIN+ > 0 V
Differential, Gain = 1: VREF > (AIN+ - AIN-) > -VREF
Multi-mode I/O pins can tolerate up to 5.8 V on the inputs, but analog signals must be less than or equal to the upper supply rail (AV+ or VDD) for proper measurement.
Input Protection
The common sources of over-voltage or under-voltage conditions include:
· Electro-Static Discharge (ESD)
· Amplifiers operating from separate supplies
· Hot-swapping board connections (connecting or disconnecting while the board is still powered)
Analog inputs can be protected from over- and under-voltage conditions using clamping diodes or current-limiting resistors, as shown below:
Please see the article in the 'Related Articles' section for more information.
Input Settling Time
The input to the SAR ADC “looks like” a single-pole RC filter. Each sample must have adequate time in the Tracking phase to allow enough settling time on the Sampling Capacitor:
The required settling time (in seconds) for a given level of accuracy is given by the following equation:
ln (2n / SA) * (RMUX + RSOURCE) * CSAMPLE
where:
SA = Settling Accuracy (% of one LSB)n = ADC Resolution in Bits
Settling time can be maximized by:
· Using “Normal” tracking mode so the ADC is tracking whenever it's not converting.
· Increasing the time between successive conversions.
It is also important to change the multiplexer and PGA settings (if needed) to allow for the maximum settling time. The best time to modify the ADC multiplexer and PGA settings is during a conversion when the sampling capacitor is disconnected from the analog input, but it is also acceptable to change these settings while the ADC is tracking if there is enough time before the conversion begins. The worst case occurs when the multiplexer and PGA settings are changed right before a conversion is initiated.
Application Note AN119 'Calculating Settling Time for Switched Capacitor ADCs' has more information on settling time. Application notes can be found on the Silicon Laboratories Applications webpage: https://www.silabs.com/products/mcu/Pages/ApplicationNotes.aspx.Single-Ended versus Differential
Single-Ended measurements are where the analog ADC input is measured with respect to ground. Single-ended measurements use a single external pin (AIN+)so that:
ADC Input = AIN+ - AGND
With single-ended measurements, the maximum input is VREF (so ADC Input = (AIN+ - AGND) = VREF) and the minimum input is 0 V (so ADC Input = (AIN+ - AGND) = 0 V). The C8051Fxxx SAR ADCs in single-ended mode use unipolar output with unsigned binary notation (so the maximum value for a 12-bit ADC in single-ended mode is 0x0FFF).
Differential measurements are where two inputs are measured with respect to each other. These types of measurements use two external pins (AIN+ and AIN-)so that:
ADC Input = AIN+ - AIN-
With differential measurements, the maximum difference between the inputs is VREF (so that ADC Input = (AIN+ - AIN-) = VREF) and the minimum difference between the inputs is -VREF (so that ADC Input = (AIN+ - AIN-) = -VREF). The C8051Fxxx SAR ADCs in differential mode use bipolar output in two's complement binary notation (so the maximum value for a 12-bit ADC in differential mode is 0x07FF).
For example, if AIN+ = 1 V and AIN- = 2V, the differential measurement is -1 V.
Miscellaneous C8051Fxxx SAR ADC Features
Window Comparator
The Window Comparator is a unique feature available on most of the Silicon Laboratories microcontroller devices. The Window Comparator automatically monitors the ADC output without CPU intervention and generates an interrupt only when the ADC output falls inside or outside a specified range (set by using the Window Comparator 'greater-than' or 'less-than' registers). This interrupt is a separate interrupt source from the other ADC interrupts and can be used in conjuction with the normal ADC interrupts or as a polled flag.
In the following example, the 'less-than' register is set to a higher value than the 'greater-than' register. In this case, the interrupt will be generated (if enabled) when the input is between the two values (less than the 'less-than' register but greater than the 'greater-than' register).
In the next example, the 'greater-than' register is set to a higher value than the 'less-than' register, so an interrupt will be generated (if enabled) when the ADC input is above the 'greater-than' threshold or below the 'less-than' threshold.
Programmable Gain Amplifier (PGA)
Many of the C8051Fxxx microcontrollers include a programmable gain amplifier in the ADC. This PGA can be used to increase the dynamic range on low-amplitude inputs. The PGA is implemented by scaling the SAR DAC output so that a signal of ½ VREF into the DAC results in a 2x gain on the input signal. This allows the PGA to improve the gain without changing the effective input impedance.
The higher gain ranges in the PGA produce more output noise, but techniques like oversampling and averaging can help reduce the noise. Application Note AN118 'Improving ADC Resolution by Oversampling and Averaging' contains more information on using these techniques. Application notes can be found on the Silicon Laboratories Applications webpage: https://www.silabs.com/products/mcu/Pages/ApplicationNotes.aspx.
High-Voltage Difference Amplifier (HVDA)
Some C8051Fxxx devices, like the C8051F040, also feature the High-Voltage Difference Amplifier (HVDA). The HVDA inputs can tolerate +/- 60 V and can be used to measure fully differential signals up to +/- 30 V. The HVDA has programmable settings that allow for the attenuation or gain of the input signal. The HVDA can be used to measure high differential voltages, reject high common-mode voltages up to +/- 60 V, and condition the signal voltage range to be suitable for input to the SAR ADC. The HVDA should be used with the ADC in differential mode for optimal performance.
Common C8051Fxxx SAR ADC QuestionsDirect-Memory Access (DMA)
Some C8051Fxxx devices, like the C8051F060, include a Direct-Memory Access (DMA) peripheral. With the DMA, the ADC conversion results can be sent directly into XDATA space without firmware intervention. The DMA does not initiate conversions; instead, it simply collects and stores the ADC output as directed.
The DMA can be programmed to accept conversion output from multiple ADCs in any sequence. The DMA is controlled through a series of pre-programmed instructions to minimize CPU usage and automatically repeats the instructions for single conversions or pre-programmed conversion sequences any number of times. In effect, the DMA can be given a programmable 'state machine' for collecting samples. The DMA also has flexible interrupt scheduling.
Q: I always see 0x0FFF at the output of my 12-bit ADC. What is the problem?
A: There are several reasons why this might occur. The ADC may be in single-ended mode, and the input voltage to the ADC is too high. Another possibility is the voltage reference to the ADC is not properly configured.
Q: If the ADC input is limited to AV+, then what is the 0.5x PGA gain range for?
A: While not providing measurement beyond the supply rails, the 0.5x gain range does allow for the measurement of signals above VREF. The 0.5x gain range can also be useful if the voltage reference used is less than ½ of AV+.
Q: When adding up the minimum tracking time and the minimum conversion time, it appears that the ADC can actually go a bit faster than your specification. Can it?
A: The ADC is capable of operating at slightly higher speeds. However, the ADC parameters are tested and specified at the maximum sample rate listed in the datasheet, and specifications cannot be guaranteed at higher sampling rates.
Q: When I change the ADC MUX channel, I do not get the correct results from the ADC. It appears that the channels are interfering with one another. Why?Q: Can I apply 5 V to the ADC input?
A: In most cases, no. The current exceptions to this rule are the HVDA inputs and the multi-mode pins on some devices. On multi-mode pins, the ADC will only measure accurately if the voltage on the analog inputs is within the supply rails. Applying voltages beyond the supply rails on analog-only input pins is a common cause of CMOS latch-up. Clamping diodes and current-limiting resistors can be used to help prevent over-voltage conditions.
Q: I am applying 2.1 V to the ADC input, but the code I get back from the ADC corresponds to 2.0 V. Why?
A: One explanation is that variations in the reference voltage will cause variations in the transfer function of the ADC. In this case, the voltage reference may be higher than expected. Another possible cause is the ADC may have some offset and/or gain error. Check the appropriate datasheet to see whether the measured error is within the specified limits. Alternatively, the SAR clock for the ADC may be too fast, which is causing problems with the SAR DAC settling time.
A: This is likely to be the result of inadequate tracking or settling time for the conversion. Make certain that the MUX switching occurs at the best possible time (during a conversion when the sampling capacitor is disconnected from the analog input). Depending on the source impedance of the signals, it may also be necessary to slow down the sample rate or buffer the input signals. In some cases, poor layout techniques can lead to capacitive AC coupling, or 'crosstalk' between ADC inputs. To prevent this from occurring, try to keep the sensitive signals from running parallel to one another on the PCB.
Related Articles
Maximum SAR sampling rate
ADC Input Voltage Range