This ensures that the timing will be exact and the maximum ADC bandwidth will be used while preserving the original 200 Hz sampling periods. The last state in the state machine causes an extra conversion to occur, but this data is ignored. This state is intended to collect the last data from the set from Channel 8.
When the Timer2 interrupt occurs, ADC0 and ADC2 will begin converting the sampled values for Channel 1. Since the ADCs are converting and the ADC sampling capacitor is no longer connected to the input, the analog input MUX can be switched to Channel 2. By doing this, this means that immediately after conversion, the ADCs will begin tracking the next channel. With SAR ADCs, the accuracy of the ADC increases along with the length of time the ADC is tracking the input, so maximizing this tracking time is important.
The ADC results for both ADC0 and ADC2 are available in the next Timer2 interrupt. The end-of-conversion flag does not need to be used since, by definition, both ADCs must be finished converting by the time the next Timer2 ISR is entered (since the maximum bandwidth of ADC0 is 100 ksps, it must be finished and have adequate tracking time for the next conversion 10 μs after the first conversion).
The following figure displays the Timer method:
This solution addresses both potential issues with the polling method and both maximizes ADC throughput and minimizes the required CPU bandwidth.
The above method applies, as well, if only one ADC is being used to sample multiple channels.