Answer

When configured as an SPI master device, the maximum C8051 SPI clock frequency that can be realized is dependent on the system clock frequency (SYSCLK).  For most devices, the maximum SPI clock frequency is one half of the system clock, but cannot exceed 12.5 MHz.  Thus, as long as system clock frequency is 25 MHz or higher, the SPI clock can operate up to 12.5 MHz, and at system clock speeds below 25 MHz, the maximum SPI clock rate is SYSCLK/2. 

When the SPI is configured in slave mode (i.e. the SCK is driven by the master), the maximum data transfer rate is 1/10 of the slave system clock frequency for most devices, provided that the SPI clock, NSS, and data lines are driven synchronously by the master.  If these signals are asynchronous with respect to the slave device, the data transfer rate must be less than 1/10 the system clock frequency of the slave device.

For specific information on a device, consult the SPI documentation in the device data sheet or reference manual.