1) What deposition process is used for the Sn plating (electroplate, immersion, or hot dip)?
2) What is the thickness of the Sn plating?
3) Is the Sn plating subjected to an annealing process after deposition with the purpose of mitigating Sn whiskers?
4) If the Sn plating is annealed after plating, is the plating tested according to JESD 201?
5) On packages that have a pad to designate pin 1, are those pads also Sn plated?
1) The deposition process used is electroplating.
2) Thickness of the electroplating is a minimum of 10 µm.
4) No. JESD 201 does not apply to components with bottom-only terminations where the full plated surface is wetted during assembly (for example: QFN and BGA components, Flip Chip bump terminations).