The I2C module include transmit and receive FIFOs to help increase throughput in faster applications, and the I2CSLAVE0 FIFO sizes are 2 bytes for TX, 2 bytes for RX.

An I2CSLAVE0 interrupt will be generated when the WR is set in the I2C0STAT register. And the WR interrupt will be set by hardware on the 9th SCL falling edge when one of the following conditions are met: 
- The I2C0 Slave responds with an ACK, and the RX FIFO is full. 
- The I2C0 Slave responds with a NACK, and the RX FIFO is full. 
- The current byte transaction has a matching I2C0 Slave address, the 8th bit was a WRITE bit (0), and FACS is set to 1. 
This bit will set the I2C0INT bit and generate an interrupt, if enabled. Software must clear this bit. 

Because the FIFO length of I2C Rx is 2, so the WR bit will only be set for every three byte receiving, but not be set for every one byte receiving.

So need to monitor the “RXE” flag of I2C0FCN1 for every one byte receiving with the setting of RFRQE(Read Request Interrupt Enable) is true, and RXTH(RX FIFO Threshold) is 0.

Detailed example code as below,

 while((I2C0FCN1 & I2C0FCN1_RXE__BMASK) == I2C0FCN1_RXE__NOT_EMPTY) { // Read data out
 I2C_DATA = I2C0DIN; // This example only supports host write 1 byte to slave
 // If want slave to accept more than 1 byte, use a buffer to save the data from FIFO
 DATA_READY = 1;
 }