I wish to use the EFM8/C8051 voltage DAC in an application, but I require that the output voltage to be 0 V at start-up (as is possible with some dedicated I2C DAC devices).  Is this possible using the EFM8/C8051 devices?


Though it is not possible for the GPIO pins to power on at 0V due to device reset values, it is possible to ensure that the pins assigned to DAC functionality power up at ~0 V by using an appropriately sized external pull-down resistor.


By default, all of the GPIO pins, including those that are accessible to the crossbar and those that aren't, have weak pull-up transistors. These weak pull-up transistors are all affected by the state of the WEAKPUD pin (XBRn.7), and are enabled on reset.  Thus, there will be an unavoidable period of time before firmware re-configures the pins where the GPIO pin voltage will be equal to VDD/VIO.  Because of the reset conditions, it is not possible to ensure that the DAC pins power-on at zero volts.  After reset, these pins can be switched to analog mode by clearing the corresponding bits in the PxMDIN register and setting the associated bit in the Px latch register soon after reset. This will disable the high and low drivers, as well as the weak pull-up transistor for these pins.


To determine the size of the needed pull-down resistor for the desired power-on voltage for the pin, you must calculate the equivalent series resistance (ESR) of the internal pull-up transistor.  The ESR value of the weak pull-up transistor is dependent on the value of VIO (or VDD if the device has no separate VIO power domain). You can calculate the ESR of this pull-up based on the datasheet specification for Weak Pull-Up Current (weak pull-up on, Vin = 0V) and VIO. Assuming VIO = 3.3V, the ESR = 3.3V/20 uA = approximately 165 k-ohms. Here is a link to a knowledge base article that discusses the ESR of the weak pullups:

For example, to keep the DAC pin below 2 V at power-on in this case, you would need to use a pull-down resistor at least as strong as 253 k-ohms. Similarly, using a 1K pull-down in this case would yeild an approximate power-on voltage of 20 mV for the selected pin.


Please note that on the EFM8LB1 and EFM8BB3 devices, it is possible to set the DAC output to persist through any reset except a POR by setting the RSTMD bit in the DACnCF0 register. Similarly, "firmware may configure the port I/O, DAC outputs, and precision reference to maintain state through system resets other than power-on resets. Setting the RSTMD bits in the DACnCF0 registers will cause the DAC output voltage and precision reference to persist through all resets except for power-on resets. Setting the PINRSTMD bit in the PCON1 register will cause the port I/O state to persist through all resets except for power-on resets." (EFM8BB3 Reference Manual section 9.3.1, page 72). Upon, POR, however, all register and RAM settings will return to their default/reset values.


Because the GPIO pins on these MCUs are multi-function I/O and not exclusively dedicated to DAC output, the port I/O configuration is defined by this weak pull up and default I/O configuration.  This may help explain why the pins do not power up at 0V as may other dedicated DAC IC devices.

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