The I2C peripheral contains separate two-byte FIFOs for RX and TX paths, and the shift registers for I2C Write and Read transfers is also separate.
All of the received data will be stored in the RX FIFO and reading the I2C0DIN register can read data from RX FIFO until RXE is set to 1, indicating that there is no more data in the RX FIFO. All of the transmit data should be transferred into the TX FIFO by writing I2C0DOUT. The hardware sets the TXNF bit to 1, which indicates that there is more room available in the TX FIFO.
After receiving START+ADDRESS+W, the RX FIFO will not be flushed by I2C0SLAVE hardware, and the data still exist in the RX FIFO until reading the I2C0DIN register to read data from RX FIFO.
Figure below describes the RX FIFO structure of the I2C slave peripheral. This FIFO consists of 2 bytes and a 1-byte shift register. If the RX FIFO is full, after receiving a new byte, the I2C0INT bit will be set to 1 to generate an interrupt because a write (WR) event occurs.
For example, if there are 31 bytes be transferred from the I2C master to I2C slave successfully, and the 30th and 31st still exist in the RX FIFO. After receiving the next START+ADDRESS+W, the RX FIFO will not be flushed, and the receiving of 32rd byte will trigger I2C0 interrupt with a WR event.
Figure 1.1. RX FIFO & SHIFT register
After receiving START+ADDRESS+R, the TX FIFO will also not be flushed by I2C0SLAVE hardware, and the first byte in the TX FIFO will be shifted to the shift register.
The following figure displays the TX FIFO structure of the I2C slave peripheral. This FIFO consists of 2 bytes and a 1-byte shift register. The data in the first FIFO byte will be shifted to the shift register when a read operation occurs.
For example, if there are 31 bytes be transmitted from the I2C slave to the master successfully before STOP, and the 32rd byte has been shifted to the shift register, the TX FIFO has been filled with the 33rd and 34th bytes. After receiving the next START+ADDRESS+R, the 33rd byte will be shifted to the shift register.
Figure 1.2. TX FIFO & SHIFT register