The EFM8BB3 and EFM8LB1 devices contain features to enable the retention of static DAC output and DAC configuration non-power on resets (POR). The DAC retention features are configured by setting the RSTMD bits in the DACnCF0 registers, which will cause the DAC output voltage and precision reference to persist through all resets except for power-on resets. Setting the DACnCF0.RSTMD bit causes the retention of the DAC SFR values and the output voltage on the DAC pin corresponding to the DACnH : DACnL data registers. Any waveform generation that was the result of firmware or other hardware modules on the device working to update the DAC would require firmware to reconfigure any hardware modules or firmware algorithms responsible for the waveform generation (i.e. updating the DACnH : DACnL data registers) after the non-POR reset.