What are the synchronization implications of controlling the WDT (which runs off the low-frequency oscillator in the LFOSC0 clock domain) with writes to the WDTCN register via the MCU core (which runs in the SYSCLK domain)?
A synchronization delay of slightly more than 2 LFOSC0 clock cycles (worst case) is required for the write to WDTCN from the SYSCLK domain to propagate to the WDT counter in the LFOSC0 domain. Hence, your application should accommodate a 3 LFO clock cycle delay between writing to WDTCN and that write taking effect.
This means you should enforce a wait of 3 LFO clock cycles after issuing a WDT DISABLE command before assuming the WDT to be in the disabled state. Similarly, plan to issue a WDT RESET (i.e. "feed", "pet", etc.) at least 3 LFO clock cycles before the actual expiration of a running WDT in order for the reset to take effect before the WDT triggers a system reset. See KB article "Updating the Watchdog configuration on EFM8" for additional considerations when writing to WDTCN.
Note that the LFOSC0 clock is subject to the internal divider (configured by OSCLD, "Internal L-F Oscillator Divider Select", in LFO0CN).