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      • Temperature Sensor Architecture, C8051, SiM3

        BrianL | 12/342/2014 | 09:58 PM

        Temperature Sensor Architecture used on Silicon Labs 8-bit and Precision 32 MCUs:

        The temperature sensors on most Silicon Labs 8-bit and SiM3 MCUs use a similar architecture, with only minor differences in implementation from one product to another.   A block diagram of this sensor is shown in the figure below.  The core of the sensor is a circuit that generates a voltage that is proportional to absolute temperature (VPTAT); this voltage is then buffered and made available as an input to the SAR ADC, which can provide a digital representation of this value to the CPU.

         

        Untitled.png

         

        This circuit makes use of the fact that the difference in the base-emitter voltages of two bipolar junction transistors operated at different current densities is proportional to absolute temperature.   The base-emitter voltage of a bipolar transistor is given by

         

        VBE = (kT/q)*ln(IC / IS),

         

        Where k is Boltzmann’s constant (1.38 × 10-23 m2 kg s-2 K-1), T is temperature (Kelvin), q is the electron charge (1.602 × 10-19 coulombs), IC is the collector current, and IS is the saturation current.  The saturation current is a property of the particular bipolar transistor used, and it tends to vary considerably with normal manufacturing variations, though two bipolar transistors formed adjacent to one another on the same piece of silicon will have saturation currents that match to a high degree of accuracy.  The saturation current is also strongly temperature-dependent.  However, the difference in VBE voltages between two matching bipolar transistors operating at different current densities (defined as the collector-emitter current divided by the area of the base-emitter junction) is given by

         

        ΔVBE = (kT/q)*[ln(IC1 / IS) – ln(IC2 / IS)]

        = (kT/q)*ln(IC1 / IC2)

         

        Thus the ΔVBE term does not include the saturation current; it is proportional to absolute temperature, and it also depends on two constants and on the ratio between two current densities, which can be accurately controlled on a single die.

        In the diagram, Q2 has an emitter-base junction area that is n times larger than that of Q1; therefore, its current density is n times smaller than that of Q1, and its base-emitter voltage will be lower.  Note that since Q1 and Q2 are PNP bipolar transistors, their base-emitter voltages are actually negative, but for simplicity this document uses the term VBE to refer to the absolute value of the base-emitter voltage.  If p-channel mosfets M1 and M2 are the same size, then the core amplifier will ensure that currents I1 and I2 are equal, which will result in a voltage equal to ΔVBE being applied across resistor R2, as shown.  This circuit actually has two stable operating points.  The first is the desired operating point, when I1 and I2 have the same non-zero value, maintained by feedback.  The second is a non-desired operating point, when I1 and I2 are both zero.  The startup circuit ensures that I1 and I2 are conducting some current, which will then cause the feedback loop to take over and set the bias voltages and currents at the desired operating point.

        Since ΔVBE is applied across R2,

         

        I2 = ΔVBE / R2

         

        By scaling the size of M3 and the value of R3, we can effectively amplify ΔVBE:

         

        VPTAT = I2*(M3/M2)*R3

        =VBE / R2)*(M3/M2)*R3

        = ΔVBE * (M3/M2)*(R3/R2),

         

        where M3 and M2 here refer to the W/L ratios of mosfets M3 and M2.  If resistors R3 and R2 are made from the same material and are located near each other, than any temperature variation in their resistance will cancel.  Therefore, VPTAT is directly proportional to ΔVBE, meaning that it is proportional to absolute temperature.  The buffer amplifier ensures that this voltage is not disturbed by the switching action of the input stage of the ADC.

        While nearly all Silicon Labs 8-bit and SiM3 MCUs use this architecture, the Precision Temperature Sensor included on the C8051F39x/37x MCUs uses a completely different architecture.   However, the F39x/37x MCUs also include a second temperature sensor that operates much the same way as the sensor described in this document.

      • UART / RS232 required clock accuracy

        BrianL | 12/342/2014 | 09:57 PM

        Question

        What is the maximum % clock error that RS232 / UART can handle before failing? What is the minimum accuracy required?

        Answer

        For asynchronous communication, like RS232, since the two devices that are communicating are synchronized at the beginning of the transmission, the total error only needs to be small enough to keep the error of the last bit sample to +/- 1/2 of a bit. Any more than this, and the last bit will be effectively sampled on the previous or following bit, causing an error. This error rate depends on the length of the transmission.

        For RS232, or UART, these transmissions are usually ten bits long - one start bit, 8 bits of data, and a stop bit. In this case, the error can be a maximum of 1/2 bit in 10 bits, or 5%. This is total error, however. If both devices have an error of more than 2.5%, the total error can be over 5% and cause a failure. In general, this "per device error" is usually rounded down from 2.5% to 2%, to provide a safer margin. Additionally, if more bits are being sent, the allowable error percentage will decrease.

        For more information, see this link: http://www.robotroom.com/Asynchronous-Serial-Communication-2.html

      • 'F93x/'F92x/'F91x/'F90x Minimum RTC Operating Voltage

        Tabitha | 12/341/2014 | 05:07 PM

        Question

        What is the minimum operating voltage for the RTC on the 'F93x, 'F92x, 'F91x, and 'F90x devices? 

        Answer

        The minimum operating voltage for RTC is 0.9 V.

         

        The RTC is split into two supply domains: the analog portion always remains on VBAT, while the digital portion switches between VBAT (in sleep mode) and the 1.8 V regulated supply (in active mode).  Note that when the digital portion is in sleep mode, the frequency is ~32 kHz, so it can operate from a low-voltage supply.

         

        Whenever the RTC registers are read or written from firmware (which can happen at 25 MHz), the VDD supply must be above the VDD monitor threshold (~1.75 V).  The same is true for the PMU and SRAM: the supply must be above the VDD monitor threshold for any interaction between those blocks and the central digital core.

      • Keil uVision IDE Hanging when Starting a Debug Session

        Tabitha | 12/341/2014 | 04:52 PM

        Question

        I installed Keil uVision and the IDE is hanging when I attempt to start a debug session.  I'm using Windows 8 x64.  What is wrong?

        Answer

        This issue appears to be very rare, and the root cause is still unknown.  In both cases of this happening, moving the Keil uVision IDE installation from C:\Keil to another location (C:\Program Files, for instance) resolved the problem.  Please contact Keil support for additional assistance.

      • C8051F120 Code Banking with Keil uVision

        Tabitha | 12/341/2014 | 04:40 PM

        Question

        How do I use code banking on the 'F120 with the Keil uVision IDE?

        Answer

        1. Once the code banking is turned on the compiler / linker will no longer generate a single *.HEX but three *.H01, *.H02, *H03.
        2. Do not assign a SW - Module to Bank 0.
        3. Include the a51 - Files from the example in http://www.silabs.com/Support%20Documents/Software/an130sw.zip. These are configured for the 'F120 using the common and 3 Banks.
        4. After the Connect command, the IDE will update to access all 4 banks.
        5. In the Download Hex File / Go / Stop tab, an additional Bank# pull down menu activates.
        6. Choose the "*.H01" file in the Download Filename dialog of the said tab.
        7. Choose "common+Bank1" in the Bank # pull down menu.
        8. Select the Erase all Code Space before Download checkbox.
        9. Trigger a download using the button.
        10. Uncheck the Erase all Code Space before Download checkbox.

        Once the first file is downloaded, perform steps 6-7 for each code bank.  Using the Erase all Code Space before Download option erases all banks independently what bank is selected, so use it with the first bank downloaded and then uncheck it.

      • 'F5xx Export Licenses

        Tabitha | 12/341/2014 | 03:51 PM

        Question

        Since the clock speed of the core on the 'F5xx devices exceeds 40 MHz, is a license required to export these devices?

        Answer

        The 'F5xx devices use license exception ENC when exporting out of the US, so a license is not required.

      • Using a Voltage Divider on an ADC Input

        Tabitha | 12/341/2014 | 03:48 PM

        Question

        I plan to measure a voltage higher than VREF with the ADc and want to use a voltage divider.  What is the highest value I can use for the resistors?

        Answer

        The main limitation on source resistance is in meeting the minimum tracking time requirement of the ADC, so if you can tolerate a longer tracking time when sampling the input voltage, you can use high-value resistors. The required settling time is for the ADC is:

         

        t = ln(2^10/SA) * RTOTAL * CSAMPLE

         

        where SA is the required settling accuracy (in LSBs), RTOTAL is the total input resistance to the ADC (= RMUX + RDIVIDER/2), and CSAMPLE is the sampling capacitance. Typical values for RMUX and CSAMPLE are given in the data sheet.  In the case of the 'F96x, it's 5 kohms and 30 pF, respectively.

         

        If we assume that the required settling accuracy is 0.5 LSBs, plug in the data sheet values for RMUX and CSAMPLE , and solve this equation for RDIVIDER, we get:

        RDIVIDER = 2*[t/((ln(2^10/0.5) * (30 pF) ) – (5k ohms)] = 2*[t / (2.287e-10) – 5k ohms]

         

        So, if you allocated 10 us for the settling time, then the maximum value of RDIVIDER is about 77 kohms. Note that RDIVIDER is the value of each of the two resistors in your divider, so the total divider resistance can be 154k ohms, and the current drain through this divider would be about 28 uA, assuming a 4.3 V input.

         

        If you instead allocate 100 us for the settling time, then the maximum value for RDIVIDER is about 865 kohms, and the current through the divider would be about 2.5 uA.

         

        We recommend keeping the value of the divider resistances to less than 1 Mohm in order to prevent inaccuracies due to leakage current on the input pin. Also, please note that high values of source resistance will make the input more susceptible to interference from coupled noise.