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      • How about the status of I2C0SLAVE FIFO after receiving START+ADDRESS+W or START+ADDRESS+R ?

        yucheng | 05/143/2017 | 05:41 AM

         

        The I2C peripheral contains separate two-byte FIFOs for RX and TX paths, and the shift registers for I2C Write and Read transfers is also separate.

         

        All of the received data will be stored in the RX FIFO and reading the I2C0DIN register can read data from RX FIFO until RXE is set to 1, indicating that there is no more data in the RX FIFO. All of the transmit data should be transferred into the TX FIFO by writing I2C0DOUT. The hardware sets the TXNF bit to 1, which indicates that there is more room available in the TX FIFO.

         

        After receiving START+ADDRESS+W, the RX FIFO will not be flushed by I2C0SLAVE hardware, and the data still exist in the RX FIFO until reading the I2C0DIN register to read data from RX FIFO.

        Figure below describes the RX FIFO structure of the I2C slave peripheral. This FIFO consists of 2 bytes and a 1-byte shift register. If the RX FIFO is full, after receiving a new byte, the I2C0INT bit will be set to 1 to generate an interrupt because a write (WR) event occurs.

        For example, if there are 31 bytes be transferred from the I2C master to I2C slave successfully, and the 30th and 31st still exist in the RX FIFO. After receiving the next START+ADDRESS+W, the RX FIFO will not be flushed, and the receiving of 32rd byte will trigger I2C0 interrupt with a WR event.

         

        RX.png

        Figure 1.1. RX FIFO & SHIFT register

         

        After receiving START+ADDRESS+R, the TX FIFO will also not be flushed by I2C0SLAVE hardware, and the first byte in the TX FIFO will be shifted to the shift register.

        The following figure displays the TX FIFO structure of the I2C slave peripheral. This FIFO consists of 2 bytes and a 1-byte shift register. The data in the first FIFO byte will be shifted to the shift register when a read operation occurs.

        For example, if there are 31 bytes be transmitted from the I2C slave to the master successfully before STOP, and the 32rd byte has been shifted to the shift register, the TX FIFO has been filled with the 33rd and 34th bytes. After receiving the next START+ADDRESS+R, the 33rd byte will be shifted to the shift register.

         

        TX.png

        Figure 1.2. TX FIFO & SHIFT register

      • EFM8LB1 I2C Slave High speed mode Introduce

        yucheng | 05/125/2017 | 05:40 AM

         

        The I2C Slave interface of EFM8LB1 is a 2-wire, bidirectional serial bus that is compatible with the I2C Bus Specification 3.0. It is capable of transferring in high-speed mode (HS-mode) at speeds of up to 3.4 Mbps, and fully downward compatible with slower speed devices.

        It also supports clock stretching for cases where the core may be temporarily prohibited from transmitting a byte or processing a received byte during an I2C transaction.

         

        By default, the I2C bus operates at speeds of up to Fast-mode (F/S mode) only, where the maximum transfer rate is 400 kbps. And it will switch from F/S mode to HS-mode only with the following sequence:

        1. START bit (S)
        2. 8-bit master code (0000 1XXX)
        3. NACK bit (N)

        The HS-mode master codes (0x08 – 0x0F) are reserved 8-bit codes which are not used for slave addressing or other purposes.

        The HS-mode compatible I2C master will switch the I2C bus to HS-mode by transmitting the above sequence at a transfer rate of not more than 400 kbps. After that, it will transfer data at a rate of up to 3.4 Mbps. And the I2C bus will switch back to F/S mode when the I2C master transmits a STOP bit.

        10.png

         

        As below is the High Speed (HS) exercise of EFM8LB1 with the I2C master JI-300. The I2C slave example code can be get after installing the Simplicity Studio.

        C:\SiliconLabs\SimplicityStudio\v4\developer\sdks\8051\v4.0.3\examples\EFM8LB1_SLSTK2030A\I2C_Slave

         

        After setting up the basic environment, a set of messages and instruction should be added to the Message List of master JI-300 to exercise the EFM8LB1 in HS-Mode.

        Four types will be added: two I2C messages – Read and Write, and two instructions – HS-Mode Set and Comment. Please refer to the JI-300 user manual for the detailed steps for how to add the messages.

        http://www.jupiteri.com/JI-300_Files/JI_JI-300.html

         

        To expedite data entry, please just use the attached setup file “JI300_efm8lb1.ser” to load the message list. The figure as below illustrated the meaning of each message and instruction.

        11.png

         

        In the exercise, the default setting of master code is “0x08”. As below is the captured signal, which show that the transfer rate for the sequence is 400 kbps.

         

        12.png

         

        After transmitting the above sequence, master will switch to HS-mode to transfer data at a rate of up to 3.4 Mbps. For example, set the Frequency of master JI-300 to 2.0M, the transfer rate will switch from 400 kbps to 2.0 Mbps.

         

        13.png

         

        14.png

         

        Since the I2C bus will switch back to F/S mode when the I2C master transmits a STOP bit, so please just remove the STOP bit for all messages following the HS-mode Set instruction to support continue data transfers.