Why does the datasheet say the Fast Mode (400 KHz Class) SMBus has a maximum operating frequency of 255 kHz?
The SMBus peripheral is internally clocked at 3 times the target bit rate and generates clock low from 1 clock cycle and clock high from 2 clock cycles.
The SMBus 400 kHz fast speed specifies clock low must be at least 1.3 us. So 1/(3x1.3us) = 256 kHz. If you set the SCL frequency to higher than 256 kHz, then the clock low time will be less than 1.3 us and violate the spec.
In practice, many I2C devices will work fine above 256 kHz, but the device will be in violation of the timing requirements, so full compatibility can't be guaranteed for strict systems.
I am trying to use ADC on the C8051F35x and am having problems figuring out how the offset DAC works.
First of all, I am not sure if the offset DAC is added to or subtracted from the AIN+ and AIN- inputs such that it has the effect of level-shifting, is applied to only one input, or even if its doing the opposite on both inputs (half the value subtracted from AIN+ and half value added to AIN-, which would cancel any offset completely.
Also, application note AN217, which has the same block diagram as the 'F35x datasheet...
...shows that the offset should be applied before the gain, but in my tests it seems to be done afterwards.
From what I can tell, the offset voltage is substracted after the amplification. Is this expected behavior, or am I doing something wrong?
As the customer has noted, there appears to be a notable difference in how the offset DAC behaves relative to the PGA, and, in this case, the customer is correct: the offset DAC operates after the PGA. So, for starters, the block diagram above should be modified as follows:
Furthermore, consistent with the customer's experiments, the ODAC output is subtracted from AIN+ and added to AIN- as a signed value, where bit 7 and bits [6:0] of the ADC0DAC register represent the sign value (0 = positive, 1 = negative) and the magnitude, respectively.