Yes.  You can send the CSP data to a UART and connect that to a host PC (for example, using one of our USB to UART interface devices).  You will need to select the com port under "dedicated serial ports" in the popup that appears when you select "Use device" in CSP.  You will need to make sure your serial settings (baud, data, stop, parity) match the settings of the UART.  Also make sure the COM port is not opened by any other program when you connect (such as a terminal program).

One point to keep in mind while using the ADC in autoscan mode being triggered by the external pin (CNVSTR) is to make sure that the Single Trigger enable is not set to 1. Setting STEN = 1 would imply that a single trigger is required to complete the whole autoscan sequence. But, the motivation for having an external conversion start is to get a sample at an exact instance of time while the idea behind having scan mode is to measure contiguous channels. Since these are mutually exclusive requirements, external convert start is not supported in single trigger mode. 

If STEN is set to 1 and the ADC is used with external convert start to autoscan channels, then the external channel will  trigger the ADC intermittently. For example - 

 

If a software/hardware redesign is not possible, one alternative that can be used in this case is to trigger a timer with the external convert and use that timer overflow to trigger the ADC in single trigger mode. 

During production, the LFOSC on EFM8 devices is calibrated to 80kHz such that we can guarantee it will oscillate at a frequency no less than the minimum (75 kHz) and no greater than the maximum (85 kHz) specification across the full temperature and supply range given in the datasheet.  This factory calibration is implemented by tuning the reset value of OSCLF - the Internal LF Oscillator Frequency Control bitfield (in the LFO0CN register).  After reset, firmware is allowed to adjust OSCLF (decreasing the value - toward 0000b - increases the LFOSC0 oscillation frequency, while increasing the value - toward 1111b - decreases the realized frequency).  Firmware may want to do this to implement finer compensation for voltage and temperature shifts than is guaranteed by our datasheet-specified limits (75/85kHz). 

However, doing so requires a known timebase against which firmware can calibrate the LFOSC by making small adjustments to OSCLF and observing the change in LFOSC oscillation frequency relative to the known timebase.  Adjusting OSCLF from the factory-calibrated reset value is therefore only useful when used in a feedback loop (where the effect of changes in OSCLF on LFOSC frequency are tracked and used to inform whether additional changes to OSCLF are necessary).  The EFM8 provides a hardware-supported technique for this task, as described in the Clocking and Oscillators section of the datasheet:

Calibrating LFOSC0

On-chip calibration of the LFOSC0 can be performed using a timer to capture the oscillator period, when running from a known timebase. When a timer is configured for L-F Oscillator capture mode, a rising edge of the low-frequency oscillator’s output will cause a capture event on the corresponding timer. As a capture event occurs, the current timer value is copied into the timer reload registers. By recording the difference between two successive timer capture values, the low-frequency oscillator’s period can be calculated. The OSCLF bits can then be adjusted to produce the desired oscillator frequency.

The calibrated reset value of OSCLF varies from device to device, and so does the "stepsize" of OSCLF LSBs.  In fact, the stepsize will likely vary on a single device from one end of the OSCLF range to the other.  In other words, there is no guarantee of what impact a change in OSCLF will have on a device's LFOSC frequency (other than the fact that increasing OSCLF slows down the oscillator, and decreasing OSCLF will speed it up).  For this reason, firmware should not change OSCLF outside of a feedback loop as described above, because doing so will introduce an unknown change in LFOSC0 frequency (which has impact to the WDT errata, discussed in "WDT_E101 - Restrictions on Watchdog Timer Refresh Interval").

 

Note: for information on the similar procedure for the Low-Frequency Oscillator on C8051Fxxx devices, see the KB article "Calibrate Internal Oscillator"

This project was designed as a proof of concept for controlling a segment LCD display through bit-banging on a low-cost, and low-pin MCU. The concept for this was introduced by this TI appnote: http://www.ti.com/lit/an/slaa654a/slaa654a.pdf

The LCD used in this project is a 4-digit, 4-mux display, PN: LCD-S401M16KR from Lumex. This LCD has 4 mux lines and 8 segment lines, for the control of up to 24 segments (7 segment digit x 4, plus colon and three dots).

The schematic and board layout files for this expansion board are provided in the attached zip file. Also included is a project for the EFM8BB1 STK that samples the voltage from the joystick and displays this voltage on the LCD.

Question: 

Are there any restrictions that impact when the Watchdog Timer (WDT) can be configured?

 

Answer:

Yes. The WDT should be DISABLED before changing the WDT configuration.  Hence, before locking out the WDT disable feature or updating the WDT timeout interval, you must ensure the WDT has first been disabled. 

See KB article "Synchronization when writing to Watchdog Timer Control (WDTCN) on EFM8" for insight on when you can be certain the WDT is disabled.

Question: 

What are the synchronization implications of controlling the WDT (which runs off the low-frequency oscillator in the LFOSC0 clock domain) with writes to the WDTCN register via the MCU core (which runs in the SYSCLK domain)?

 

Answer:

A synchronization delay of slightly more than 2 LFOSC0 clock cycles (worst case) is required for the write to WDTCN from the SYSCLK domain to propagate to the WDT counter in the LFOSC0 domain.  Hence, your application should accommodate a 3 LFO clock cycle delay between writing to WDTCN and that write taking effect.

This means you should enforce a wait of 3 LFO clock cycles after issuing a WDT DISABLE command before assuming the WDT to be in the disabled state.  Similarly, plan to issue a WDT RESET (i.e. "feed", "pet", etc.) at least 3 LFO clock cycles before the actual expiration of a running WDT in order for the reset to take effect before the WDT triggers a system reset.  See KB article "Updating the Watchdog configuration on EFM8" for additional considerations when writing to WDTCN.

Note that the LFOSC0 clock is subject to the internal divider (configured by OSCLD, "Internal L-F Oscillator Divider Select", in LFO0CN).

Question

What is SMBus free timeout? What is the behavior of SMBus after the free timeout occurs?

 

Answer

The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus is designated as free.

The SMBus Free Timeout detection on 8-bit MCUs can be enabled by setting the SMBFTE (or SMBnFTE) bit. When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods. A clock source which is determined by the SMBus clock setting (the SMBCS bit field in SMB0CF ) is required for free timeout detection, even in a slave-only implementation.

 

When a Free Timeout is detected, the interface will respond as if a STOP was detected. For a matched slave address, the Free Timeout sets STO flag and generates an interrupt, the interrupt must be cleared by firmware.

If the Free Timeout condition happens after STOP detection but before servicing the STOP status flag, then STOP bit gets cleared by the Free Timeout, but the SI interrupt flag is not affected.

If the Free Timeout condition happens after STOP detection and servicing, then the STOP status flag will not be set by the Free Timeout condition.