After locking code space using the lock byte, I am unable to connect to my JTAG MCU (eg C8051F020, C8051F120) using the Flash Utility or IDE. Is this the expected behavior?
Answer
For MCUs with a JTAG interface, it is not possible to connect to the device using the Flash Utility or IDE after locking the code space. To restore debug access, the device must be erased (ie "erase code space" in the Flash Utility or IDE).
For MCUs with a C2 interface, it is possible to connect to the device using the Flash Utility or IDE after locking the code space, however, the flash can not be read. Attempting to read locked flash will result in 0x00.
What does "K" mean in the C8051F120-TB-K part number?
Answer
We recently updated the legacy kit naming convention. The C8051F120-TB is the board only and the C8051F120-TB-K is the kit which includes the C8051F120-TB plus the box with the quick start card.
The SMBus module of EFM8 devices can support master, slave, and multi-master modes. When SMBus operating as a master, the SMBus clock source can be selected by SMBCS bit field, it can be Timer 0/1 Overflow or Timer 2 High/Low Byte Overflow.
The overflows from the selected clock source will determine both the bit rate and the absolute minimum SCL low and high times. The device will hold the SCL line low for 1 overflow period, and release it for 2 overflow periods. The THIGH is typically twice as large as TLOW, of course, the actual SCL output may vary due to other devices on the bus.
So the selected clock source should typically be configured to overflow at 3 times the desired bit rate, for example, if desire 100K SMBus bit rate, the overflow rate of the selected clock source should be 300KHz. The figure below illustrate how to generate the SCL by the timer source overflows.
For example, select the Timer 1 overflow as the SMBus clock source, configure the Timer 1 as 8-bit Counter/Timer with Auto-Reload (mode 2), and select the timer 1 clock source as system clock divided by 4.
The overflow rate of Timer 1 in 8-bit auto-reload mode is below.
If set the TH1 with 0xEC, the Ftimer1 will be around 300KHz with 24.5MHz system clock divided by 4.
The finial SMBus bit rate will be Ftimer/3, around 102Kbps.
To register a license for Keil C51, two components are needed - a CID (Computer ID) and PSN (Product Serial #). The CID is different from computer to computer, so you cannot simply copy the license information from one computer to another.
If a computer cannot access the Internet, we can obtain its PSN/CID and register it with another computer that can access the Internet. The CID and PSN can be obtained in one of the following ways:
If Keil uVision is installed, the CID can be seen on the registration page under [File] > [License Management]. For details, see AN104: http://www.silabs.com/Support%20Documents/TechnicalDocs/an104.pdf
If Studio is installed, you can obtain both the CID and PSN. In Studio, select [Help] > [Licensing] > [Keil 8051 ...] then click "this form" to start the registration page. Then, in the browser's address bar and in the fields of the form, you can see both the PSN and CID.
With both the PSN and CID, register for a license here: https://www.keil.com/license/install.htm. The license (LIC) can be installed under Studio, back in the Licensing Helper ([Help] > [Licensing] > [Keil 8051 ...]), or in Keil uVision under [File] > [License Management].
Electromagnetic compatibility (EMC) optimization is a core competence of Silicon Labs. As well as implementing chip-level circuits to improve performance in a system, we have a very strong understanding of board-level design to ensure best-in-class EMC performance. We have helped many customers optimize PCBs to meet emissions standards and use our EMC lab to help solve our customers' board-level emissions problems.
Optimizing Chip-Level EMC Performance
EMC determines the ability of a product like MCU to coexist in its intended electromagnetic environment without causing or suffering functional degradation or damage to itself or to other devices that may reside in that environment – it neither is susceptible to nor causes Electromagnetic Interference (EMI). Since EMC involves the presence of a source of electromagnetic radiation, a receptor of that electromagnetic radiation and a path for that electromagnetic radiation, it is only necessary to remove two of these to achieve acceptable EMC. In general, it is not practical to completely eliminate electromagnetic radiation from a digital integrated circuit. However, by incorporating many fundamental techniques to control electromagnetic emissions from an integrated circuit and to then incorporate new methodology to reduce “leakage” of these emissions outside of the chip. From the overall system point of view, it is always more cost effective to design a product with suppression at the integrated circuit level as opposed to addressing these issues at the PCB or system level .
System Level Considerations
By designing our MCUs with EMC optimization in mind, Silicon Labs delivers solutions that reduce system level noise and interference. The following resources will enable designers to better understand system level considerations to reduce EMI, how to measure it and how to ‘design-it-out', of your PCB designs.
Most electronic products require radiated EMI testing to ensure that they don't interfere with other RF systems, such as television and radio broadcast and cell phones. After meeting the required standards, an endorsement from a calibrated and certified EMI test house is issued. A TEM cell allows companies like Silicon Labs (who are in the semiconductor or product business, not the EMI testing business) do "pre-compliance" testing before going to a certified test house. The TEM cell along with an EMI receiver or spectrum analyzer comprise a system capable of making calibrated radiated field strength measurements. The TEM cell acts as a calibrated antenna and shielded enclosure, which both captures the radiated energy and blocks outside signals from the measurement. The spectrum analyzer is the receiver, which, with custom software, measures and displays the frequencies emitted and their strengths.
In the 8-bit SDK, the capsense library has been updated from SDK versions 4.08 to 4.09. This update primarily changed how capsense thresholds are assigned. Previously, threshold values were global - one set of threshold values applied to all capsense inputs. This works fine for situations where all capsense inputs are approximately the same size, but it is incompatible with systems with varying capsense input button sizes, or for situations where different thresholds are needed on a per-button basis.
This change was reflected in Hardware Configurator.
Previously, the global thresholds were located in the Capsense Library peripheral screen:
Now, the individual thresholds are located in each pin's settings, in the Port I/O tab.
The settings that were moved are: Average Touch Delta, Active Threshold, and Inactive Threshold.
On the Application Note webpage, the example code is organized by topic, such as ADC or UART. Check the beginning of the application note to determine if the application note is applicable to your MCU.
If the IDE is installed to the default directory, the example code is installed at:
C:\SiLabs\MCU\Examples
In the Examples directory, the example code is organized by the MCU family. There are over 1000 pieces of example code currently available in this directory.
Where can I find Ethernet examples for Silicon Labs MCUs?
Answer
Ethernet examples for the 'F12x and the 'F34x are attached to this article. These are the lowest layer, hardware-level routines intended to be interfaced with a Ethernet stack.
8-bit Knowledge Base
Can not connect to JTAG MCU after locking
Question
After locking code space using the lock byte, I am unable to connect to my JTAG MCU (eg C8051F020, C8051F120) using the Flash Utility or IDE. Is this the expected behavior?
Answer
For MCUs with a JTAG interface, it is not possible to connect to the device using the Flash Utility or IDE after locking the code space. To restore debug access, the device must be erased (ie "erase code space" in the Flash Utility or IDE).
For MCUs with a C2 interface, it is possible to connect to the device using the Flash Utility or IDE after locking the code space, however, the flash can not be read. Attempting to read locked flash will result in 0x00.
Meaning of 'K' in the new C8051 target boards
Question
What does "K" mean in the C8051F120-TB-K part number?
Answer
We recently updated the legacy kit naming convention. The C8051F120-TB is the board only and the C8051F120-TB-K is the kit which includes the C8051F120-TB plus the box with the quick start card.
How to calculate the SMBus clock rate of EFM8 devices?
The SMBus module of EFM8 devices can support master, slave, and multi-master modes. When SMBus operating as a master, the SMBus clock source can be selected by SMBCS bit field, it can be Timer 0/1 Overflow or Timer 2 High/Low Byte Overflow.
The overflows from the selected clock source will determine both the bit rate and the absolute minimum SCL low and high times. The device will hold the SCL line low for 1 overflow period, and release it for 2 overflow periods. The THIGH is typically twice as large as TLOW, of course, the actual SCL output may vary due to other devices on the bus.
So the selected clock source should typically be configured to overflow at 3 times the desired bit rate, for example, if desire 100K SMBus bit rate, the overflow rate of the selected clock source should be 300KHz. The figure below illustrate how to generate the SCL by the timer source overflows.
For example, select the Timer 1 overflow as the SMBus clock source, configure the Timer 1 as 8-bit Counter/Timer with Auto-Reload (mode 2), and select the timer 1 clock source as system clock divided by 4.
The overflow rate of Timer 1 in 8-bit auto-reload mode is below.
If set the TH1 with 0xEC, the Ftimer1 will be around 300KHz with 24.5MHz system clock divided by 4.
The finial SMBus bit rate will be Ftimer/3, around 102Kbps.
Registering Keil C51 on a computer without internet access
To register a license for Keil C51, two components are needed - a CID (Computer ID) and PSN (Product Serial #). The CID is different from computer to computer, so you cannot simply copy the license information from one computer to another.
If a computer cannot access the Internet, we can obtain its PSN/CID and register it with another computer that can access the Internet. The CID and PSN can be obtained in one of the following ways:
With both the PSN and CID, register for a license here: https://www.keil.com/license/install.htm. The license (LIC) can be installed under Studio, back in the Licensing Helper ([Help] > [Licensing] > [Keil 8051 ...]), or in Keil uVision under [File] > [License Management].
Electromagnetic Interference (EMI) and Electromagnetic Compatibility (EMC)
Chip Level Design Considerations
Optimizing System EMC Performance
Electromagnetic compatibility (EMC) optimization is a core competence of Silicon Labs. As well as implementing chip-level circuits to improve performance in a system, we have a very strong understanding of board-level design to ensure best-in-class EMC performance. We have helped many customers optimize PCBs to meet emissions standards and use our EMC lab to help solve our customers' board-level emissions problems.
Optimizing Chip-Level EMC Performance
EMC determines the ability of a product like MCU to coexist in its intended electromagnetic environment without causing or suffering functional degradation or damage to itself or to other devices that may reside in that environment – it neither is susceptible to nor causes Electromagnetic Interference (EMI). Since EMC involves the presence of a source of electromagnetic radiation, a receptor of that electromagnetic radiation and a path for that electromagnetic radiation, it is only necessary to remove two of these to achieve acceptable EMC. In general, it is not practical to completely eliminate electromagnetic radiation from a digital integrated circuit. However, by incorporating many fundamental techniques to control electromagnetic emissions from an integrated circuit and to then incorporate new methodology to reduce “leakage” of these emissions outside of the chip. From the overall system point of view, it is always more cost effective to design a product with suppression at the integrated circuit level as opposed to addressing these issues at the PCB or system level .
System Level Considerations
By designing our MCUs with EMC optimization in mind, Silicon Labs delivers solutions that reduce system level noise and interference. The following resources will enable designers to better understand system level considerations to reduce EMI, how to measure it and how to ‘design-it-out', of your PCB designs.
EMI Design Resources
World-Class EMC Testing Capabilities
Most electronic products require radiated EMI testing to ensure that they don't interfere with other RF systems, such as television and radio broadcast and cell phones. After meeting the required standards, an endorsement from a calibrated and certified EMI test house is issued. A TEM cell allows companies like Silicon Labs (who are in the semiconductor or product business, not the EMI testing business) do "pre-compliance" testing before going to a certified test house. The TEM cell along with an EMI receiver or spectrum analyzer comprise a system capable of making calibrated radiated field strength measurements. The TEM cell acts as a calibrated antenna and shielded enclosure, which both captures the radiated energy and blocks outside signals from the measurement. The spectrum analyzer is the receiver, which, with custom software, measures and displays the frequencies emitted and their strengths.
EFM8SB1 Capsense Library / Configurator update
In the 8-bit SDK, the capsense library has been updated from SDK versions 4.08 to 4.09. This update primarily changed how capsense thresholds are assigned. Previously, threshold values were global - one set of threshold values applied to all capsense inputs. This works fine for situations where all capsense inputs are approximately the same size, but it is incompatible with systems with varying capsense input button sizes, or for situations where different thresholds are needed on a per-button basis.
This change was reflected in Hardware Configurator.
Previously, the global thresholds were located in the Capsense Library peripheral screen:
The settings that were moved are: Average Touch Delta, Active Threshold, and Inactive Threshold.
复位时 Port I/O 状态
问题
端口I/O引脚在设备复位时状态是怎样的?
答案
在任何复位源(比如把复位引脚拉低)确认阶段，所有端口I/O引脚默认配置为数字输入且弱上拉状态。
English version: Port I/O State at Reset
Keil uVision查看不同存储器的值
问题
Keil uVision debug MCU时，如何查看直接寻址的片内RAM、间接寻址的片内RAM、扩展的外部RAM和代码存储空间 ?
答案
使用Keil uVision对MCU进行debug时，可通过其memory窗口查看不同存储器的值。
以debug EFM8UB2为例，
查看直接寻址的片内RAM时，在memory窗口输入D:0x00, 即可以查看从0x00地址开始的直接寻址的片内RAM的值
查看间接寻址的片内RAM时，在memory窗口输入I：0x00
查看扩展的外部RAM，在memory窗口输入X:0x0000
查看代码存储区域时，在memory窗口输入C:0x0000
建议在debug时使用Silabs推出的Simplicity Studio V4, 其界面更为直观，debug更为高效。
MCU Example Code
Question
Where can I find example code for the C8051xxxx MCU?
Answer
Example code for Silicon Labs's MCUs is available in two main locations.
The first is the Application Note webpage:
https://www.silabs.com/products/mcu/Pages/ApplicationNotes.aspx
On the Application Note webpage, the example code is organized by topic, such as ADC or UART. Check the beginning of the application note to determine if the application note is applicable to your MCU.
Example code is also part of the Silicon Labs IDE. The Silicon Labs IDE is available for download at:
https://www.silabs.com/products/mcu/Pages/SoftwareDownloads.aspx
If the IDE is installed to the default directory, the example code is installed at:
C:\SiLabs\MCU\Examples
In the Examples directory, the example code is organized by the MCU family. There are over 1000 pieces of example code currently available in this directory.
Ethernet Examples
Question
Where can I find Ethernet examples for Silicon Labs MCUs?
Answer
Ethernet examples for the 'F12x and the 'F34x are attached to this article. These are the lowest layer, hardware-level routines intended to be interfaced with a Ethernet stack.