During production, the LFOSC on EFM8 devices is calibrated to 80kHz such that we can guarantee it will oscillate at a frequency no less than the minimum (75 kHz) and no greater than the maximum (85 kHz) specification across the full temperature and supply range given in the datasheet.  This factory calibration is implemented by tuning the reset value of OSCLF - the Internal LF Oscillator Frequency Control bitfield (in the LFO0CN register).  After reset, firmware is allowed to adjust OSCLF (decreasing the value - toward 0000b - increases the LFOSC0 oscillation frequency, while increasing the value - toward 1111b - decreases the realized frequency).  Firmware may want to do this to implement finer compensation for voltage and temperature shifts than is guaranteed by our datasheet-specified limits (75/85kHz). 

However, doing so requires a known timebase against which firmware can calibrate the LFOSC by making small adjustments to OSCLF and observing the change in LFOSC oscillation frequency relative to the known timebase.  Adjusting OSCLF from the factory-calibrated reset value is therefore only useful when used in a feedback loop (where the effect of changes in OSCLF on LFOSC frequency are tracked and used to inform whether additional changes to OSCLF are necessary).  The EFM8 provides a hardware-supported technique for this task, as described in the Clocking and Oscillators section of the datasheet:

Calibrating LFOSC0

On-chip calibration of the LFOSC0 can be performed using a timer to capture the oscillator period, when running from a known timebase. When a timer is configured for L-F Oscillator capture mode, a rising edge of the low-frequency oscillator’s output will cause a capture event on the corresponding timer. As a capture event occurs, the current timer value is copied into the timer reload registers. By recording the difference between two successive timer capture values, the low-frequency oscillator’s period can be calculated. The OSCLF bits can then be adjusted to produce the desired oscillator frequency.

The calibrated reset value of OSCLF varies from device to device, and so does the "stepsize" of OSCLF LSBs.  In fact, the stepsize will likely vary on a single device from one end of the OSCLF range to the other.  In other words, there is no guarantee of what impact a change in OSCLF will have on a device's LFOSC frequency (other than the fact that increasing OSCLF slows down the oscillator, and decreasing OSCLF will speed it up).  For this reason, firmware should not change OSCLF outside of a feedback loop as described above, because doing so will introduce an unknown change in LFOSC0 frequency (which has impact to the WDT errata, discussed in "WDT_E101 - Restrictions on Watchdog Timer Refresh Interval").

Note: for information on the similar procedure for the Low-Frequency Oscillator on C8051Fxxx devices, see the KB article "Calibrate Internal Oscillator"

This project was designed as a proof of concept for controlling a segment LCD display through bit-banging on a low-cost, and low-pin MCU. The concept for this was introduced by this TI appnote: http://www.ti.com/lit/an/slaa654a/slaa654a.pdf

The LCD used in this project is a 4-digit, 4-mux display, PN: LCD-S401M16KR from Lumex. This LCD has 4 mux lines and 8 segment lines, for the control of up to 24 segments (7 segment digit x 4, plus colon and three dots).

The schematic and board layout files for this expansion board are provided in the attached zip file. Also included is a project for the EFM8BB1 STK that samples the voltage from the joystick and displays this voltage on the LCD.

Question: 

Are there any restrictions that impact when the Watchdog Timer (WDT) can be configured?

Answer:

Yes. The WDT is a low energy peripheral and has multiple timing requirements. Additionally the WDT logic requires certain sequences to safely change interval or modify the configuration.

First, The WDT should be DISABLED before changing the WDT configuration. Hence, before locking out the WDT disable feature or updating the WDT timeout interval, you must ensure the WDT has first been disabled. 

Second, synchronization delays apply when writing to the WDT register. See KB article Synchronization when writing to Watchdog Timer Control (WDTCN) on EFM8.

Third, If you intend to change the WDT interval, care must be taken to feed the WDT before disabling, as the WDT can trigger a reset when the interval is changed. This can happen even if the WDT is disabled. In order to avoid synchronization issues, the advised sequence is as follows.

void change_interval()  
{    
WDTCN = 0xA5;          // Refresh WDT    
// Insert code to wait for 2 divided LFOSC0 clock periods    
WDTCN = 0xDE;          // Disable WDT (first key)    
WDTCN = 0xAD;          // Disable WDT (second key)    
// Insert code to wait for 3 divided LFOSC0 clock periods    
WDTCN = WDT_interval   // Change the current WDT interval to a lower interval with the MSB cleared to 0    
// Insert code to wait for 1 SYSCLK clock period } 

Question: 

What are the synchronization implications of controlling the WDT (which runs off the low-frequency oscillator in the LFOSC0 clock domain) with writes to the WDTCN register via the MCU core (which runs in the SYSCLK domain)?

Answer:

A synchronization delay of slightly more than 2 LFOSC0 clock cycles (worst case) is required for the write to WDTCN from the SYSCLK domain to propagate to the WDT counter in the LFOSC0 domain.  Hence, your application should accommodate a 3 LFO clock cycle delay between writing to WDTCN and that write taking effect.

This means you should enforce a wait of 3 LFO clock cycles after issuing a WDT DISABLE command before assuming the WDT to be in the disabled state.  Similarly, plan to issue a WDT RESET (i.e. "feed", "pet", etc.) at least 3 LFO clock cycles before the actual expiration of a running WDT in order for the reset to take effect before the WDT triggers a system reset.  See KB article "Updating the Watchdog configuration on EFM8" for additional considerations when writing to WDTCN.

Note that the LFOSC0 clock is subject to the internal divider (configured by OSCLD, "Internal L-F Oscillator Divider Select", in LFO0CN).

Question

How to use EFM8LB1/EFM8BB3 I2C slave, it looks quite different from SMBus peripheral. 

Answer

The EFM8LB1/BB3 contains a I2C slave peripheral, it includes many interesting features which helps on high speed transfer but may cause confusion to the user who was familiar with legacy SMBus operation.  Here we make a brief intro of I2C slave, and attach an I2C slave bootloader example code for reference. This code example has been written for EFM8BB3 but can be easily ported to EFM8LB1 if needed. 

The I2C peripheral contains 2 bytes FIFO and 1 byte shift register for TX/RX individually. The I2C slave support auto ACK/NACK an I2C master, it is controlled by BUSY bit field of I2C0CN0 register.  In default, the BUSY is "1" which the device will not respond  to an I2C master. All I2C data sent to the device will be NACKed. We should set this BUSY bit as "0", the device will acknowledge an I2C master. For a case, the master keep sending data to device, the device ACK the master automatically for max 3 ACKs since two bytes in FIFO and 1 byte in shift register. And then the SCL is hold low to indicate device is not capable to receive more data.  We should check  RXE bit field of I2C0FCN1 register to know if there is data in FIFO, read received data from I2C0DIN register.

The auto ACK feature makes difficulty on flow control, as we mentioned above, the SCL is hold low when the RX FIFO is full, so that device can handle the data. What about the master changes read/write direction? There is another feature can helps on this situation. The FACS bit field of I2C0ADM register. The defaults value is "1" which means FORCE_STRETCH. When this bit is set, clock stretching always occurs after an ACK of the address byte until firmware clears I2C0INT bit. With this clock stretching feature, we are able to hand the flow control during read/write direction changes.

There is an I2C slave bootloader example code which base on AN945, please take a look into it and have a reference on how the I2C slave state machine works. The I2CSlave state machine is described in two Flow Diagrams in the Reference Manual (Fig 17.7 and Fig 17.8) and can be condensed down to this Status Decoding table (Table 17.1 in the Reference Manual - https://www.silabs.com/documents/public/reference-manuals/efm8bb3-rm.pdf)

The I2C Bootloader is designed to work just like the SMBus Bootloader which is described in detail in AN945 - https://www.silabs.com/documents/public/application-notes/an945-efm8-factory-bootloader-user-guide.pdf. The boot_I2C.c file in the attachment shows how the I2CSlave peripheral is being used - one may notice that only three states are defined in the code while the Table shown above describes a lot more. There are a couple of reasons why some states are not included in the Bootloader code - 

1. The Bootloader code is written in such a way that some of the cases described above will never occur or even if they do, they can be bundled together in a default case. We are mostly concerned with RD, WR and RD+NACK states. 
2. The Bootloader's code is restricted by size. We try to fit it into one Flash page and that, in turn, means that we include code that is only absolutely necessary for the Bootloader to function and not account for cases that will never occur.