During production, the LFOSC on EFM8 devices is calibrated to 80kHz such that we can guarantee it will oscillate at a frequency no less than the minimum (75 kHz) and no greater than the maximum (85 kHz) specification across the full temperature and supply range given in the datasheet.  This factory calibration is implemented by tuning the reset value of OSCLF - the Internal LF Oscillator Frequency Control bitfield (in the LFO0CN register).  After reset, firmware is allowed to adjust OSCLF (decreasing the value - toward 0000b - increases the LFOSC0 oscillation frequency, while increasing the value - toward 1111b - decreases the realized frequency).  Firmware may want to do this to implement finer compensation for voltage and temperature shifts than is guaranteed by our datasheet-specified limits (75/85kHz). 

However, doing so requires a known timebase against which firmware can calibrate the LFOSC by making small adjustments to OSCLF and observing the change in LFOSC oscillation frequency relative to the known timebase.  Adjusting OSCLF from the factory-calibrated reset value is therefore only useful when used in a feedback loop (where the effect of changes in OSCLF on LFOSC frequency are tracked and used to inform whether additional changes to OSCLF are necessary).  The EFM8 provides a hardware-supported technique for this task, as described in the Clocking and Oscillators section of the datasheet:

Calibrating LFOSC0

On-chip calibration of the LFOSC0 can be performed using a timer to capture the oscillator period, when running from a known timebase. When a timer is configured for L-F Oscillator capture mode, a rising edge of the low-frequency oscillator’s output will cause a capture event on the corresponding timer. As a capture event occurs, the current timer value is copied into the timer reload registers. By recording the difference between two successive timer capture values, the low-frequency oscillator’s period can be calculated. The OSCLF bits can then be adjusted to produce the desired oscillator frequency.

The calibrated reset value of OSCLF varies from device to device, and so does the "stepsize" of OSCLF LSBs.  In fact, the stepsize will likely vary on a single device from one end of the OSCLF range to the other.  In other words, there is no guarantee of what impact a change in OSCLF will have on a device's LFOSC frequency (other than the fact that increasing OSCLF slows down the oscillator, and decreasing OSCLF will speed it up).  For this reason, firmware should not change OSCLF outside of a feedback loop as described above, because doing so will introduce an unknown change in LFOSC0 frequency (which has impact to the WDT errata, discussed in "WDT_E101 - Restrictions on Watchdog Timer Refresh Interval").

Note: for information on the similar procedure for the Low-Frequency Oscillator on C8051Fxxx devices, see the KB article "Calibrate Internal Oscillator"

Question: 

Are there any restrictions that impact when the Watchdog Timer (WDT) can be configured?

Answer:

Yes. The WDT should be DISABLED before changing the WDT configuration.  Hence, before locking out the WDT disable feature or updating the WDT timeout interval, you must ensure the WDT has first been disabled. 

See KB article "Synchronization when writing to Watchdog Timer Control (WDTCN) on EFM8" for insight on when you can be certain the WDT is disabled.

Question: 

What are the synchronization implications of controlling the WDT (which runs off the low-frequency oscillator in the LFOSC0 clock domain) with writes to the WDTCN register via the MCU core (which runs in the SYSCLK domain)?

Answer:

A synchronization delay of slightly more than 2 LFOSC0 clock cycles (worst case) is required for the write to WDTCN from the SYSCLK domain to propagate to the WDT counter in the LFOSC0 domain.  Hence, your application should accommodate a 3 LFO clock cycle delay between writing to WDTCN and that write taking effect.

This means you should enforce a wait of 3 LFO clock cycles after issuing a WDT DISABLE command before assuming the WDT to be in the disabled state.  Similarly, plan to issue a WDT RESET (i.e. "feed", "pet", etc.) at least 3 LFO clock cycles before the actual expiration of a running WDT in order for the reset to take effect before the WDT triggers a system reset.  See KB article "Updating the Watchdog configuration on EFM8" for additional considerations when writing to WDTCN.

Note that the LFOSC0 clock is subject to the internal divider (configured by OSCLD, "Internal L-F Oscillator Divider Select", in LFO0CN).