The SMBus module of EFM8 devices can support master, slave, and multi-master modes. When SMBus operating as a master, the SMBus clock source can be selected by SMBCS bit field, it can be Timer 0/1 Overflow or Timer 2 High/Low Byte Overflow.
The overflows from the selected clock source will determine both the bit rate and the absolute minimum SCL low and high times. The device will hold the SCL line low for 1 overflow period, and release it for 2 overflow periods. The THIGH is typically twice as large as TLOW, of course, the actual SCL output may vary due to other devices on the bus.
So the selected clock source should typically be configured to overflow at 3 times the desired bit rate, for example, if desire 100K SMBus bit rate, the overflow rate of the selected clock source should be 300KHz. The figure below illustrate how to generate the SCL by the timer source overflows.
For example, select the Timer 1 overflow as the SMBus clock source, configure the Timer 1 as 8-bit Counter/Timer with Auto-Reload (mode 2), and select the timer 1 clock source as system clock divided by 4.
The overflow rate of Timer 1 in 8-bit auto-reload mode is below.
If set the TH1 with 0xEC, the Ftimer1 will be around 300KHz with 24.5MHz system clock divided by 4.
The finial SMBus bit rate will be Ftimer/3, around 102Kbps.
Keil uVision debug MCU时，如何查看直接寻址的片内RAM、间接寻址的片内RAM、扩展的外部RAM和代码存储空间 ?
建议在debug时使用Silabs推出的Simplicity Studio V4, 其界面更为直观，debug更为高效。
Most of the C8051 devices include an external oscillator drive circuit to driver an external crystal, ceramic resonator, capacitor, or RC network.
For a crystal or ceramic resonator configuration, the crystal/resonator must be wired across the XTAL1 and XTAL2 pins as shown in the figure below. And a 10M ohm resistor must be wired across the XTAL2 and XTAL1 pins for the crystal/resonator configuration.
The 10 M ohm resistor between XTAL1 and XTAL2 is required to provide proper DC bias to the internal crystal driver. And the parallel impedance (10M ohm) decides the loop gain. Having a larger impedance is usually desired because it will increase the loop gain, and hence reduce start up time and increase negative impedance. So it shouldn't try to reduce this 10M ohm impedance.
With regard to the unstable or unable to start up oscillation, please check the items below one by one.
1. Review the PCB layout:
Crystal oscillator circuits are quite sensitive to PCB layout.
AN203 provided a good starting point in the design and layout of a PCB, and the methods presented in this application note should be taken as suggestions.
2. Check the capacitors value connected to the crystal.
The capacitors shown in the external crystal configuration provide the load capacitance required by the crystal for correct oscillation. These capacitors are "in series" as seen by the crystal and "in parallel" with the stray capacitance of the XTAL1 and XTAL2 pins.
The desired load capacitance CL depends upon the crystal and the manufacturer. Refer to the crystal data sheet when completing these calculations below.
The equation for determining the load capacitance for two capacitors is as follows:
C is the capacitor value connected to the two crystal leads, in general, will connect a same capacitor on each lead. CS is the total stray capacitance of the PCB, and the stray capacitance for a typical layout where the crystal is as close as possible to the pins is 2-5 pF per pin.
For example, a tuning-fork crystal of 25 MHz has a recommended load capacitance of 12.5 pF. With a stray capacitance of 3 pF per pin (6 pF total), the 13 pF capacitors yield an equivalent capacitance of 12.5 pF across the crystal.
12.5 pF = C/2 + 6
C = 13 pF
3. Choose a reasonable driver level
Please refer to the KB below to choose a reasonable driver level.
The KB describe how to specify the XFCN to issue a reasonable crystal driver current considering the required Drive Level (DL) and Equivalent Series Resistance (ESR) of the crystal rather than only considering the frequency.
4. Measure the actual driver level on board
If the crystal still unstable or cannot start up after checking the items above, you should measure the actual driver level on board (Crystal vendor should be able to provide the test report). If the measured driver level is way larger than the maximum specification, the crystal will be over-driven and may result to the crystal circuit not working, and the crystal operational lifetime will be reduced.
The recommended method is adding a series resistance Rd to the crystal to reduce the driver level.
The STALL packet indicates that the endpoint has halted, or a control pipe does not support a certain request.
A function uses the STALL handshake packet to indicate that it is unable to transmit or receive data. Besides the default control pipe, all of a function's endpoints are in an undefined state after the device issues a STALL handshake packet. The host must never issue a STALL handshake packet.
Typically, the STALL handshake indicates a functional stall. A functional stall occurs when the halt feature of an endpoint is set. In this circumstance, host intervention is required via the default control pipe to clear the halt feature of the halted endpoint. Less often, the function returns a STALL handshake during a SETUP or DATA stage of a control transfer. This is called a protocol stall and is resolved when the host issues the next SETUP transaction.
As below is the captured USB bus data between an EFM8 HID device and Window PC USB host. The EFM8 HID device sends a STALL handshake in response to the get DEVICE_QUALIFIER descriptor request because the EFM8 HID device does not support the certain request. After that, the USB host will issue the next SETUP transaction.
Since the USB is a polled bus, meaning the host controller must initiate all transfers, so the behavior of USB transfers may depend on the USB host. As below is the captured bus data between the EFM8 HID device and MacOS PC, there is no any get DEVICE_QUALIFIER descriptor or other nonstandard request, so no STALL handshake can be found.