What is the maximum value to use for a GPIO pull-up resistor on EFM8SB1 under 3.3V VDD?
Maximum pull-up resistor value for EFM8SB1 is: 570k ohms
Use of an external pull-up resistor instead of the internal pull-up on an EFM8SB1 GPIO provides an opportunity for reduced current draw in certain applications, particularly in battery powered designs. The reason for this is the maximum value resistance that works as a pull-up for an EFM8SB1 GPIO pin is larger than the internal pull-up resistance listed in the EFM8SB1 datasheets (around 165k ohms), which equates to significant power savings in which one or more pull-up or pull-down resistors are frequently drawing current. The typical 165k ohm internal pull-up resistance was calculated based on the IPU data in table 4.15 of the datasheet.
R_PULL_UP = 3.3V /2 0uA = 165k ohms.
For example, a battery operated open / closed sensor switch may be required to have a pull-up on the switch circuit. The firmware may be monitoring for a high level on the switch / GPIO circuit. In the case of a normally closed switch, when the switch is engaged, the resulting circuit to ground through the switch is detected by the firmware and acted upon. Depending upon how often or how long the switch is activated, the resulting power drain through the pull-up could shorten the overall lifespan of the battery. In this type of situation, use a large value external resistor instead of the internal pull-up configuration of the GPIO pin in order to reduce the current draw and extend battery life.
To arrive at 570k ohms conclusion as the maximum safe resistor pull-up value, we first determine the GPIO maximum input leakage current. Characterization testing of Engineering IC test lots have revealed an upper limit of 1 uA for EFM8SB1 devices.
Refer to the datasheet table 4.15 for Input leakage current (ILK), Input high voltage (VIH).
Having determined the leakage current, we could then get the minimum input high voltage for the GPIO in table 4.15 under VDD operating voltage 3.3V, the value is VDD-0.6. This indicate the allowable voltage drop across the external pull-up is 0.6V. By using Ohm’s Law to divide the voltage drop of the external pull-up by the threshold leakage current value and multiplying the result by 0.95, we safely determine the appropriate pull-up resistor value with a 5% margin.
0.6 V / 0.000001 A * 0.95 = 570k ohms
Where can I find example code for the C8051xxxx MCU?
Example code for Silicon Labs's MCUs is available in two main locations.
The first is the Application Note webpage:
On the Application Note webpage, the example code is organized by topic, such as ADC or UART. Check the beginning of the application note to determine if the application note is applicable to your MCU.
Example code is also part of the Silicon Labs IDE. The Silicon Labs IDE is available for download at:
If the IDE is installed to the default directory, the example code is installed at:
In the Examples directory, the example code is organized by the MCU family. There are over 1000 pieces of example code currently available in this directory.
Where can I find Ethernet examples for Silicon Labs MCUs?
Ethernet examples for the 'F12x and the 'F34x are attached to this article. These are the lowest layer, hardware-level routines intended to be interfaced with a Ethernet stack.
For 8-bit MCU like EFM8UB2, a port pin isavailable on crossbar, do I need to enable crossbar if a port pin work as general purpose GPIO (non peripheral mode)?
For port pin is available on crossbar, if you need to control it's level through the Px.x latch value, you need to enable the crossbar.
Take the EFM8UB2 as example, you could see what port pin was available on crossbar in figure 11.4 on page 83 of the reference manual.
The port I/O cell block diagram shown in figure 11.2 on page 79 of reference manual.From the below diagram, we can know once the crossbar is disabled, the Px.x latch value wont' take effects on port pin.
What is the difference of GPIO structure on Silicon Labs MCU families.
5V tolerance of GPIO pins on Silicon Labs MCU families as followsType A:
Pins are tolerant of the IO power supply voltage plus 2.5V, so they are 5V tolerant with a 3.3V supply. When the pin voltage rises more than 2V above the supply, the leakage currents from the pin to the supply and from the pin to ground will increase with voltage. When the power supply is 0V, the applied pin voltage can be as high as 3.3V at room temperature with moderate leakage; but at that voltage, the leakage can be very high at elevated temperature.
Devices: EFM8UB1, C8051F86x. etc
Pins cannot exceed the IO power supply voltage, which can be up to 5V. The pin includes an ESD protection diode to the power supply, so the pin leakage will increase exponentially if the pin voltage exceeds the power supply voltage by more than 0.5V at room temperature. These pins are 5V tolerant only if the IO supply is 5V..
There is a statement in EFM8LB1 spec that pin leakage current is in the range of [-1.1 4] uA . Does this leakage current affects ADC result of external signal?
Correct, the leakage mainly dominated by the ESD protection circuit for the port structure. It may flow in or out of the device. The leakage current is strongly sensitive to the temperature.
Let us assume 100nA leakage, and output impedance for source signal to be measured is 10k ohm. Then the measurement error caused by the leakage likes an offset error of ADC result. This example gets 100nA*10kOhm = 1mV voltage offset (measured) on the pin.
Under condition that ADC is configured as 2.5V VFS and 12-bit resolution. Then we have 1 LSB equals to be about 2.5V/4096 = 610uV
Then the 10k Ohm resistance of external source signal to be measured would see 1 LSB offset error as 1mV>610uV.
Related KBA: Comparator Input Leakage