Hello. I have a si5324 chip with a 114.285 MHz crystal on the XA/XB pins, and a 156.25 MHz clock on the CKIN1 pins. I am 
trying to generate a "cleaned" 156.25 MHz clock on the CKOUT1 output pins. CKIN2 and CKOUT2 are left floating.

I used the DSPLLsim tool to generate the register settings, in which I have successfully configured and verified.
However, I'm getting the following results when I read the status registers:

LOSX_INT     = '0'. NORMAL
LOS1_INT     = '0'. NORMAL
LOS2_INT     = '0'. NORMAL
LOL_INT      = '1'. PLL NOT locked
FOS1_INT     = '0'. NORMAL
FOS2_INT     = '0'. NORMAL
DIGHOLDVALID = '0'. Waiting on more samples
LOL_FLG      = '1'. PLL Not Locked
FOS1_FLG     = '0'. NORMAL
FOS2_FLG     = '0'. NORMAL
ICAL         = '0'. NORMAL

Also, I am continually writing a 0x00 to register 132 to clear the latched status bits. I have waited quite a long time
for the PLL to lock (it's at least 30 min now), but it never does.

These are the settings generated from the DSPLLsim tool:

#HEADER
# Date: Tuesday, March 30, 2021 3:01 PM
# File Version: 3
# Software Name: Precision Clock EVB Software
# Software Version: 5.1
# Software Date: July 23, 2014
# Part number: Si5324
#END_HEADER
#PROFILE
# Name: Si5324
#INPUT
# Name: CKIN
# Channel: 1
# Frequency (MHz): 156.250000
# N3: 4993
# Maximum (MHz): 177.187500
# Minimum (MHz): 151.562500
#END_INPUT
#INPUT
# Name: CKIN
# Channel: 2
# Frequency (MHz): 114.285688
# N3: 3652
# CKIN2 to CKIN1 Ratio: 14285711 / 19531250
# Maximum (MHz): 129.599188
# Minimum (MHz): 110.856449
#END_INPUT
#PLL
# Name: PLL
# Frequency (MHz): 5000.000000
# XA-XB Frequency (MHz): 114.285000
# f3 (MHz): 0.031294
# N1_HS: 8
# N2_HS: 8
# N2_LS: 19972
# Phase Offset Resolution (ns): 1.60000
# BWSEL_REG Option: Frequency (Hz)
#  5:    4
#  4:    9
#  3:   18
#  2:   37
#  1:   78
#END_PLL
#OUTPUT
# Name: CKOUT
# Channel: 1
# Frequency (MHz): 156.250000
# NC1_LS: 4
# CKOUT1 to CKIN1 Ratio: 1 / 1
# Maximum (MHz): 177.187500
# Minimum (MHz): 151.562500
#END_OUTPUT
#CONTROL_FIELD
# Register-based Controls
#        FREE_RUN_EN: 0x1
#    CKOUT_ALWAYS_ON: 0x0
#         BYPASS_REG: 0x0
#          CK_PRIOR2: 0x1
#          CK_PRIOR1: 0x0
#          CKSEL_REG: 0x0
#              DHOLD: 0x0
#            SQ_ICAL: 0x1
#          BWSEL_REG: 0x5
#        AUTOSEL_REG: 0x0
#           HIST_DEL: 0x12
#              ICMOS: 0x3
#              SLEEP: 0x0
#         SFOUT2_REG: 0x7
#         SFOUT1_REG: 0x7
#          FOSREFSEL: 0x2
#             HLOG_2: 0x0
#             HLOG_1: 0x0
#           HIST_AVG: 0x18
#          DSBL2_REG: 0x1
#          DSBL1_REG: 0x0
#             PD_CK2: 0x0
#             PD_CK1: 0x0
#         FLAT_VALID: 0x1
#             FOS_EN: 0x0
#            FOS_THR: 0x1
#            VALTIME: 0x1
#              LOCKT: 0x1
#        CK2_BAD_PIN: 0x0
#        CK1_BAD_PIN: 0x1
#            LOL_PIN: 0x0
#            INT_PIN: 0x1
#         INCDEC_PIN: 0x1
#       CK1_ACTV_PIN: 0x0
#          CKSEL_PIN: 0x0
#        CK_ACTV_POL: 0x1
#         CK_BAD_POL: 0x1
#            LOL_POL: 0x1
#            INT_POL: 0x1
#           LOS2_MSK: 0x0
#           LOS1_MSK: 0x0
#           LOSX_MSK: 0x0
#           FOS2_MSK: 0x0
#           FOS1_MSK: 0x0
#            LOL_MSK: 0x1
#              N1_HS: 0x4
#             NC1_LS: 0x3
#             NC2_LS: 0x3
#              N2_LS: 0x4E03
#              N2_HS: 0x4
#                N31: 0x1380
#                N32: 0xE43
#         CLKIN2RATE: 0x3
#         CLKIN1RATE: 0x4
#           FASTLOCK: 0x1
#            LOS1_EN: 0x3
#            LOS2_EN: 0x3
#            FOS1_EN: 0x0
#            FOS2_EN: 0x0
#   INDEPENDENTSKEW1: 0x0
#   INDEPENDENTSKEW2: 0x0
#END_CONTROL_FIELD
#REGISTER_MAP
  0, 54h
  1, E4h
  2, 52h
  3, 15h
  4, 12h
  5, EDh
  6, 3Fh
  7, 2Ah
  8, 00h
  9, C0h
 10, 08h
 11, 40h
 19, 29h
 20, 35h
 21, FCh
 22, DFh
 23, 18h
 24, 39h
 25, 80h
 31, 00h
 32, 00h
 33, 03h
 34, 00h
 35, 00h
 36, 03h
 40, 80h
 41, 4Eh
 42, 03h
 43, 00h
 44, 13h
 45, 80h
 46, 00h
 47, 0Eh
 48, 43h
 55, 1Ch
131, 1Fh
132, 02h
137, 01h
138, 0Fh
139, FCh
142, 00h
143, 00h
136, 40h
#END_REGISTER_MAP
#END_PROFILE

Are there any mistakes in the configuration?

One more note: If I read the I2C registers immediately after I write to them, the verify comes back good (the values match), however,
after I've run the calibration, the values are automatically changed in the following registers: 31, 32, 36, 42. Is this normal
and expected?

Hello. I have a si5324 chip with a 114.285 MHz crystal on the XA/XB pins, and a 156.25 MHz clock on the CKIN1 pins. I am trying to generate a "cleaned" 156.25 MHz clock on the CKOUT1 output pins. CKIN2 and CKOUT2 are left floating.

I used the DSPLLsim tool to generate the register settings, in which I have successfully configured and verified. However, I'm getting the following results when I read the status registers:

LOSX_INT     = '0'. NORMAL
LOS1_INT     = '0'. NORMAL
LOS2_INT     = '0'. NORMAL
LOL_INT      = '1'. PLL NOT locked
FOS1_INT     = '0'. NORMAL
FOS2_INT     = '0'. NORMAL
DIGHOLDVALID = '0'. Waiting on more samples
LOL_FLG      = '1'. PLL Not Locked
FOS1_FLG     = '0'. NORMAL
FOS2_FLG     = '0'. NORMAL
ICAL         = '0'. NORMAL

Also, I am continually writing a 0x00 to register 132 to clear the latched status bits. I have waited quite a long time
for the PLL to lock (it's at least 30 min now), but it never does.

These are the settings generated from the DSPLLsim tool:

#HEADER
# Date: Tuesday, March 30, 2021 3:01 PM
# File Version: 3
# Software Name: Precision Clock EVB Software
# Software Version: 5.1
# Software Date: July 23, 2014
# Part number: Si5324
#END_HEADER
#PROFILE
# Name: Si5324
#INPUT
# Name: CKIN
# Channel: 1
# Frequency (MHz): 156.250000
# N3: 4993
# Maximum (MHz): 177.187500
# Minimum (MHz): 151.562500
#END_INPUT
#INPUT
# Name: CKIN
# Channel: 2
# Frequency (MHz): 114.285688
# N3: 3652
# CKIN2 to CKIN1 Ratio: 14285711 / 19531250
# Maximum (MHz): 129.599188
# Minimum (MHz): 110.856449
#END_INPUT
#PLL
# Name: PLL
# Frequency (MHz): 5000.000000
# XA-XB Frequency (MHz): 114.285000
# f3 (MHz): 0.031294
# N1_HS: 8
# N2_HS: 8
# N2_LS: 19972
# Phase Offset Resolution (ns): 1.60000
# BWSEL_REG Option: Frequency (Hz)
#  5:    4
#  4:    9
#  3:   18
#  2:   37
#  1:   78
#END_PLL
#OUTPUT
# Name: CKOUT
# Channel: 1
# Frequency (MHz): 156.250000
# NC1_LS: 4
# CKOUT1 to CKIN1 Ratio: 1 / 1
# Maximum (MHz): 177.187500
# Minimum (MHz): 151.562500
#END_OUTPUT
#CONTROL_FIELD
# Register-based Controls
#        FREE_RUN_EN: 0x1
#    CKOUT_ALWAYS_ON: 0x0
#         BYPASS_REG: 0x0
#          CK_PRIOR2: 0x1
#          CK_PRIOR1: 0x0
#          CKSEL_REG: 0x0
#              DHOLD: 0x0
#            SQ_ICAL: 0x1
#          BWSEL_REG: 0x5
#        AUTOSEL_REG: 0x0
#           HIST_DEL: 0x12
#              ICMOS: 0x3
#              SLEEP: 0x0
#         SFOUT2_REG: 0x7
#         SFOUT1_REG: 0x7
#          FOSREFSEL: 0x2
#             HLOG_2: 0x0
#             HLOG_1: 0x0
#           HIST_AVG: 0x18
#          DSBL2_REG: 0x1
#          DSBL1_REG: 0x0
#             PD_CK2: 0x0
#             PD_CK1: 0x0
#         FLAT_VALID: 0x1
#             FOS_EN: 0x0
#            FOS_THR: 0x1
#            VALTIME: 0x1
#              LOCKT: 0x1
#        CK2_BAD_PIN: 0x0
#        CK1_BAD_PIN: 0x1
#            LOL_PIN: 0x0
#            INT_PIN: 0x1
#         INCDEC_PIN: 0x1
#       CK1_ACTV_PIN: 0x0
#          CKSEL_PIN: 0x0
#        CK_ACTV_POL: 0x1
#         CK_BAD_POL: 0x1
#            LOL_POL: 0x1
#            INT_POL: 0x1
#           LOS2_MSK: 0x0
#           LOS1_MSK: 0x0
#           LOSX_MSK: 0x0
#           FOS2_MSK: 0x0
#           FOS1_MSK: 0x0
#            LOL_MSK: 0x1
#              N1_HS: 0x4
#             NC1_LS: 0x3
#             NC2_LS: 0x3
#              N2_LS: 0x4E03
#              N2_HS: 0x4
#                N31: 0x1380
#                N32: 0xE43
#         CLKIN2RATE: 0x3
#         CLKIN1RATE: 0x4
#           FASTLOCK: 0x1
#            LOS1_EN: 0x3
#            LOS2_EN: 0x3
#            FOS1_EN: 0x0
#            FOS2_EN: 0x0
#   INDEPENDENTSKEW1: 0x0
#   INDEPENDENTSKEW2: 0x0
#END_CONTROL_FIELD
#REGISTER_MAP
  0, 54h
  1, E4h
  2, 52h
  3, 15h
  4, 12h
  5, EDh
  6, 3Fh
  7, 2Ah
  8, 00h
  9, C0h
 10, 08h
 11, 40h
 19, 29h
 20, 35h
 21, FCh
 22, DFh
 23, 18h
 24, 39h
 25, 80h
 31, 00h
 32, 00h
 33, 03h
 34, 00h
 35, 00h
 36, 03h
 40, 80h
 41, 4Eh
 42, 03h
 43, 00h
 44, 13h
 45, 80h
 46, 00h
 47, 0Eh
 48, 43h
 55, 1Ch
131, 1Fh
132, 02h
137, 01h
138, 0Fh
139, FCh
142, 00h
143, 00h
136, 40h
#END_REGISTER_MAP
#END_PROFILE

Are there any mistakes in the configuration?

One more note: If I read the I2C registers immediately after I write to them, the verify comes back good (the values match), however, after I've run the calibration, the values are automatically changed in the following registers: 31, 32, 36, 42. Is this normal and expected?

I have looked at the sleepy bee i(efmsb1) n the past, but the datasheet the Sleep mode (sleep mode with RAM retention) lists a "typical" value of 50 nA, which is higher than the 10 nA claimed in the C8051F911 datasheet.

As for the EFP01, it's got a 150 nA quiesient current with no outputs enabled, and 300 nA with a single output enabled. Also, the efficiency drops pretty low when the load is only 10 nA.

So unless I'm misunderstanding something, your solution seems orders of magnitude worse in terms of power consumption.

If it helps, my application spends 99.999% of its time in sleep mode waiting for a GPIO event, and runs off a coin cell battery.

I have looked at the sleepy bee i(efmsb1) n the past, but the datasheet is unclear what the actual max current consumption is in Sleep mode (sleep mode with RAM retention). It lists a "typical" value of 50 nA, which is higher than the 10 nA claimed in the C8051F911 datasheet.

As for the EFP01, it's got a 150 nA quiesient current with no outputs enabled, and 300 nA with a single output enabled. Also, the efficiency drops pretty low when the load is only 10 nA.

So unless I'm misunderstanding something, your solution seems orders of magnitude worse in terms of power consumption.

If it helps, my application spends 99.999% of its time in sleep mode waiting for a GPIO event, and runs off a coin cell battery.

I noticed that the webpage for the C8051F911 says that it's not recommended for new designs. What would be an equivalent/improved part that is recommended for new designs? I think the specs that are difficult to match is the fact that it can operate down to 0.9V and has a 10 nA sleep mode with memory retention.

Greetings. I am consistently experiencing very long startup times on getting Simplicity Studio 4 to start. It seems to get stuck on the splash screen with "Loading org.eclipse.ui.forms." Sometimes if I wait for about 5 minutes the IDE will finally show up, other times it will just stall out forever, giving me a "this program is not responding" message from Windows.

Any tricks to getting a more reliable startup of this program?