Question

How should I connect the pins which are not intended to be used on Si4x6x / EZR32?

Answer

• TX: Connect to VDD (PA should be powered to avoid leakage currents)
• RXP, RXN: Connect to ground
• GPIO pins: No connect

Question

How should I connect the pins which are not intended to be used on Si106x/8x?

Answer

• TX: Connect to VDD (PA should be powered to avoid leakage currents)
• RXP, RXN: Connect to ground
• GPIO pins: No connect

Question

How can I calculate the occupied bandwidth of a digital frequency modulated signal (2FSK, 2GFSK, 4FSK, 4GFSK)?

Answer

Carson’s Rule to determine the BW for an FSK signal:

where OBW is the occupied bandwidth.

For 2FSK / 2GFSK modulation the symbol rate is equal to the data rate, and unlike 4FSK / 4GFSK modulation there is only one deviation. This way, the formula can be simplified to the following form:

4FSK / 4GFSK modulation has inner and outer deviation parameters, the connection between them can be described as the following:

This way, the OBW for 4FSK / 4GFSK:

GFSK modulation uses a Gaussian filter on the transmitter side which smoothens the shape of the frequency pulse. This results that the changes between symbols are flatter than in case of general FSK modulation which causes that higher frequency components are supressed, i.e. the bandwidth decreases. This means that a GFSK modulated signal has always got a little narrower occupied bandwidth than an FSK modulated signal.

Example: data rate = 20 kbps, deviation = 10 kHz, modulation type: 2FSK / 2GFSK.

The occupied bandwidth can be calculated based on the formula above:

For FSK modulation this formula approximately gives the real occupied bandwidth of the signal, for GFSK modulation the bandwidth also depends on the value of the B*T factor of the Gaussian filter. Using B*T = 0.5 for 2GFSK modulation, the occupied bandwidth will be always smaller than for general 2FSK modulation. In the above example the OBW for 2FSK is ~40 kHz, while for 2GFSK (B*T = 0.5) it is ~35 kHz.

Note that it is not recommended to decrease the value of the B*T factor below 0.3 as it increases inter symbol interference.

Question

I see high radiated spur within the frequency range of the Si4x6x RF chip VCO signal. How can I suppress this?

Answer

In RX only boards due to the lack of additional filtering the VCO signal might be radiated via the antenna too. In that case some filtering between the antenna and the matching balun network is recommended.

Moreover, the filtering of the traces connected to the SDN, GPIO 2, 3 pins (and the DC supply line of a TCXO) is also suggested at the VCO frequency (not only in case of RX only boards).

Use cases where applying additional filtering on SDN, GPIO 2, 3 (and the DC supply line of a TCXO) is strongly recommended:

• 2 layer PCBs (the problematic traces cannot be routed on inner layers, they can operate as hidden antennas)
• High-power (≥20dBm) applications (the level of possible spur is higher for high power parts)

The actual level of this radiated spur can vary with the actual board design.

Note: Not all Si4x6x reference designs use this additional filtering on SDN, GPIO 2, 3 (and TCXO VDD supply) lines. If possible, it is recommended to apply the additional filtering inductors on all customer designs. If BOM cost is critical, these elements can be eliminated from the design, but be aware that depending on the actual PCB layout structure, increased radiated spur in the frequency range of the VCO signal might appear.

The SDN and GPIO 2, 3 filtering on Silicon Labs reference designs is shown in the following figure:

The inductor value should be selected in a way to ensure enhanced suppression at the VCO frequency, so inductors that have SRF at the ~ 3.5 GHz frequency range. 

Question

I see high radiated spur within the frequency range of the Si4x6x RF chip VCO signal. How can I suppress this?

Answer

In RX only boards due to the lack of additional filtering the VCO signal might be radiated via the antenna too. In that case some filtering between the antenna and the matching balun network is recommended.

Moreover, the filtering of the traces connected to the SDN, GPIO 2, 3 pins (and the DC supply line of a TCXO) is also suggested at the VCO frequency (not only in case of RX only boards).

Use cases where applying additional filtering on SDN, GPIO 2, 3 (and the DC supply line of a TCXO) is strongly recommended:

• 2 layer PCBs (the problematic traces cannot be routed on inner layers, they can operate as hidden antennas)
• High-power (≥20dBm) applications (the level of possible spur is higher for high power parts)

The actual level of this radiated spur can vary with the actual board design.

Note: Not all Si4x6x reference designs use this additional filtering on SDN, GPIO 2, 3 (and TCXO VDD supply) lines. If possible, it is recommended to apply the additional filtering inductors on all customer designs. If BOM cost is critical, these elements can be eliminated from the design, but be aware that depending on the actual PCB layout structure, increased radiated spur in the frequency range of the VCO signal might appear.

The SDN and GPIO 2, 3 filtering on Silicon Labs reference designs is shown in the following figure:

The inductor value should be selected in a way to ensure enhanced suppression at the VCO frequency, so inductors that have SRF at the ~ 3.5 GHz frequency range. 

Question

How can I calculate the expected range improvement for a given extra link budget?

Answer

The range improvement can be calculated based on the following formula:

where

- ΔR is the desired value of range improvement (ratio between the new and original range)

- n is the propagation factor (the typical outdoor value is between 2.8 and 4)

- ΔLB is the link budget improvement

The ΔLB link budget improvement can be achieved with higher conducted output power, better conducted sensitivity, or with higher antenna gain either on TX or RX side.

Let’s see an example:

Assuming a ΔLB = 3 dB additional link budget improvement (e.g. the TX power is increased or RX sensitivity is improved by 3 dB) and outdoor line of sight between the transmitter and the receiver (which results ~n = 3 propagation factor), the range improvement will be the following:

Thus, for example assuming 400m original range, 3 dB higher transmitter power or 3 dB better sensitivity would result ~500m range.

Using a 2-layer PCB in the application hardware is usually preferred by customers due to cost saving purposes. Still, based on the RF output power level, unwanted radiation of top or bottom layer traces (mostly VDD or digital) can occur, which causes that the application can violate the harmonic limits of the related standards. In order to minimize the possibility of unwanted trace radiations, Silicon Labs recommends to use multilayer PCBs in the following cases:

• >=16dBm output power at sub-GHz frequencies

• >=10dBm output power at 2.4GHz

Note that the actual recommendation depends on which standard (ETSI, FCC, ARIB, etc.) the application has to be compliant with.

One can notice that not all Silicon Labs reference design follows the above listed recommendations. EZRadioPRO reference design boards are made on 2 or 4 PCB layers based on the output power, while all EZR32 and EFR32 reference design boards are using 4 or 6 PCB layers due to the complexity of the design. In the latter case, the layout routing could not be realised on a 2-layer PCB if all digital traces were intended to be used. Of course, on a custom design where the complexity of the design is much less, 2-layer PCBs can be used for EZR32 or EFR32 applications as well considering the above listed recommendations.