Si5338 PLL lock issue
Thank you for your reply. Yes, the input is ready. I also tried to use IN1/2, same issue.
Nov 10 2020, 5:04 PM
Si5338 PLL lock issue on
Clock Generator, Buffer, Crystal Oscillator Forum
I am trying to use IN5/6 as reference clock to output 148.5 MHz clock on Si5338. Based on the flow chart from Si5338 Datasheet. We need to set PLL to use FCL values after read the register map. But if we do that, the PLL will never lock. If we skip that step, it seems that the PLL can lock.
So as showed above, skip the heighted step. I don’t know whether it's ok to do that and whether it will bring in any risks. My configuration code is showed below. Could anyone kindly take a look and give me some suggestion?
Thanks a lot in advance,
Oct 18 2020, 9:50 PM