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Posted
Si5338 I2C Programming Tips on Clock Generator, Buffer, Crystal Oscillator Knowledge Base
1. A input clock or crystal should be valid before you write a new configuration (register map) to the RAM of Si5338 https://www.silabs.com/documents/public/software/AN428SW.zip 3. I2C timing: Hold Time START Condition tHD:STA should bigger than 4us for standard mode and 0.6us for fast mode. Data Hold Time tHD:DAT should bigger than 100ns for standard mode fast mode. 4. If you simulate I2C via FPGA, please configure SDA to inout. Set SDA as output when write data, and Set SDA as input when ACK send to FPGA. |
19 days ago |
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Posted
A note for a brick M64/M68/M88 recovery on Clock Generator, Buffer, Crystal Oscillator Knowledge Base
If you’re not able to communicate to your module, neither over the serial interface nor over the network, possibly due to installing the wrong update file. It requires that you use the Commander program, that you can connect to the module’s serial port and that you have access to the module’s reset or can power cycle the device. Please be noted that keep serial connection when you power cycle or reset the device. If your device/system are powered by USB that is also a serial port, you cannot plug out/plug in USB cable to power cycle the device. Because the serial connection will also be disconnected when you plug out/plug in USB cable. Please separate Serial port and power supply or use a reset signal for this case. |
19 days ago |
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Replied
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Si5383A outputs stops working/disabled
Hi Jenna, Is the issue fixed? There is a crystal mounted in EVB, so you don't need apply a clock to XA/XB SMA connector. But if the crystal was removed, please apply a clock to XA/XB SMA connector and modify the EVB according to description in User Guide. Thanks. Yong |
47 days ago |
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Adjusting Si5326 input to output phase
Hi Michael, Thanks for questions, you have dive into it deeply. No other fast methods. Do you need zero delay mode? If yes, the Si5342/44/45 series has an additional zero delay mode so the input to output skew would be low upon power up/reset/ICAL as well as when locked up. Thanks. Yong |
53 days ago |
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Si5338 PLL lock issue
Sorry for reply later. Was input signal ready when you program the Si5338? Thanks. Yong |
Oct 28 2020, 6:04 AM |
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SI5338A - when Confirm PLL lock status, it was stucked
Hi Hua,
Was the issue fixed? Thanks. Yong |
Aug 21 2020, 7:19 AM |
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Selected an answer for
Si53344 Propagation Delay
Hi Just post feedback here from SF ns of propagation delay is a typo. It's picosecond as unit. Thanks. |
Aug 18 2020, 9:25 AM |
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Si53344 Propagation Delay
Hi Just post feedback here from SF ns of propagation delay is a typo. It's picosecond as unit. Thanks. |
Aug 18 2020, 9:25 AM |
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Si5351A generating 132.8356 Hz square wave
Hi Doug, For Si5351A, 132.8356 Hz is not valid. The output must be 2.5kHz to 200MHz. Thanks. Yong |
Aug 05 2020, 1:46 AM |
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Selected an answer for
The actual clock generated by si5351a using the clock generator is larger than the set value.
It works normally when connect PIN.6 (SSEN) to ground. Thanks. |
Jul 30 2020, 7:20 AM |