Yes. The application is also monitoring voltage of a build-in Lithium battery - it is that VBAT voltage. In that case the internal 2.5V reference is used.  The purpose of battery voltage monitoring is to have an information about battery state. Based on the measured battery voltage we can estimate the remaining battery capacity (it is not precise, but it provides at lease some estimation), indicate it to the user and switch the application to a low power (shutdown) mode if the battery is too low.

I think that we can not use VMON for this purpose as it is just a comparator and it does not provide possibility to monitor external voltage, just the internal one. Am I right?

Attached is the corresponding part of schematics with slider potentiometer connection. The potentiometer has resistance of about 10 kohms and it is activated by Q2 only during the measurement period to save the battery power. Since it is connected between VDD (+2.8V) and GND the ADC result should not be influenced by VDD variation.

So far it works well. The only issue is that uncompensated ADC gain error in this configuration.

Thank you for your reply.

So it means that it is not possible to use that build-in ADC Calibration Register to compensate for ADC gain error if VDD  (AVDD) is used as a ADC reference. So I need to use a software/firmware workaround to transform the available ADC range that is different for each device (i.e. from 0 to 63831) to a required full scale range (0 to ‭65535‬) if needed. And it also means that the the final ADC resolution will be no more 16 bit but lower.

Do you have any idea how large could be the maximum value of  gain error in this configuration? Unfortunately it is not specified in the datasheet. I see that for most units it is quite small (below 1 %), but for some units it reaches value up to 3% and maybe also higher. Could it reach i.e. 10% or even higher value? If so it would reduce the final ADC resolution significantly...

I don't need a high ADC throughput in my application as the slider position is checked just few times a second, so the required calculation does not limit the final performance. The only issue I see is related to the situation when the ADC gain error is so high that the resulting ADC resolution significantly decrease below 16 bits. Could it occur?

We use internal ADC of BGM113 device (EFR32BG1) to sense position of a sliding potentiometer that is connected between VDD and GND terminals of BGM113 device. As a reference voltage for ADC conversion we selected VDD, so we would expect that the ADC output will change from value 0 to ADC_MAX if potentiometer slider is moving from the potentiometer terminal connected to GND to the opposite one connect to VDD.

Unfortunately it is not exactly so as for some units we see ADC reading just from a limited range of values i.e. from 0 to 64000 or even in a smaller range (considering a 16 bit ADC output). That would indicate a need for ADC gain calibration. 

Based on the available documentation we have understood that ADC is not calibrated from manufacturing for use with VDD reference and we need to calibrated it ourselves in our application. So we tried to calibrate ADC offset and gain based on description available in "EFR32xG1 Wireless Gecko Reference Manual" to make sure that ADC output 0 corresponds to slider position connected to GND and ADC_MAX to a slider connect to VDD.  Unfortunately it seems that even with that build in calibration routine we are not able to set  ADC gain so the potentiometer slider range is well scaled to the full scale ADC range and the calibration routine is not able to completely remove ADC gain error for some reason.

During the ADC gain calibration we see that  ADC gain / ADC output value changes if SCANGAIN and SINGLEGAIN values are modified.  The strange point is that ADC outputs maximum value for SINGLEGAIN/SCANGAIN setting to 0, then ADC output decreases with increasing gain setting up to 63 and then it starts again from a similar value as for gain 0 and decreases again with raising gain setting. So it seems that a positive gain correction possibility is missing and we are only able to decrease a ADC gain.

Below you can see an example of ADC outputs for different SINGLEGAIN/SCANGAIN settings in the situation when ADC input pin is connected to VDD and oversampling is set to x4096 so ADC produce 16 bit output value:

SINGLEGAIN / SCANGAIN        ADC output [16 bits]
0                                                  63831
1                                                  63772
2                                                  63712

…
62                                               60086
63                                               52046
64                                               63832
65                                               63769

...
126                                            60088
127                                            52047

Please could you confirm that it is an expected behavior? 

Please could you also clarify what does exactly mean the following sentence on page 77 of EFR32xG1 Wireless Gecko Reference Manual?

”For the VDD reference and external reference, there is no hardware gain calibration. Calibration can be done by software after taking a sample.”

It's only the specific evaluation kit that is being obsoleted, there are currently no plans to discontinue BGM113 or BGM111 modules.