Hi

I just want to know that for SPI Communication in 8051F120, the SPI0DAT register will reset after a byte received and read ? if it is not how can I clear the SPI0DAT before the next data receive ???

 

Hi

 

I am Configuring 8051f120 as a slave . Master is FPGA and it  will send the data to slave  when data is selected from GUI . Am getting some wrong data in slave SPI0DAT register , if am sending the data 2 or 3 times , getting the actual data. Is there any Clock Synchronization problem in slave side ??? How can I resolve this issue ???

Sorry , the Pin assignment in the attached code is wrong .it is

sbit MOSI    =    P0^4; 

sbit SCK     =     P0^2; 

 

then I am changed the code by including the Interrupt Method .

(Note: #define  ERROR_OCCURRED    0x40        // Indicator for the Slave to tell the Master an error occurred)

 

void SPI_ISR (void) interrupt 6
{
   static unsigned char ucReadData;

   if (WCOL == 1)
   {
      // Write collision occurred

      SPI0DAT = ERROR_OCCURRED;        // Indicate an error occurred
      WCOL = 0;                        // Clear the Write collision flag
   }
   else if (RXOVRN == 1)
   {
      // Receive overrun occurred

      SPI0DAT = ERROR_OCCURRED;        // Indicate an error occurred
      RXOVRN = 0;                      // Clear the Receive Overrun flag
   }
   else
   {
      // SPIF caused the interrupt

         ucReadData = SPI0DAT;            // Read the command
   }

 

  SPIF = 0;                        // Clear the SPIF flag
}

 

I am getting some data in SPI0DAT register but not the correct data . If am trying to send the data from master side 2 or 3 times,then  the correct data is getting. if it is a clock Synchronization problem ?? How to resolve it ?

Hello,

I have configured 8051F120 as a slave for SPI Communication . I am not getting the data send by Master in SPI0DAT register. Clock and data from Master out pin has been verified in Scope . Please check my code and let me know is there anything I have missed out for configuring 8051F120 as a slave . Note : sbit MOSI    =    P0^2;   
                     sbit SCK     =     P0^4; 

 

void main()
{
    /*Disable the Watchdog Timer to avoid the intermitent reset condition*/
    Disable_WDT();

    INT_Oscillator_Init();

    // change the system clock to 4 * intosc using PLL.
    PLL_Init();   

    HW_SPI_Init();

 

   SPI_Data_Read(unsigned char *);

    while(1)
    {

     }

}

unsigned char )Disable_WDT(void)
{
    //save the SFRPAGE
    //disable 8051 internal watchdog timer
    WDTCN = 0xde;                       
    WDTCN = 0xad;    
    //Return Success
    return (unsigned char)SUCCESS;
}

char INT_Oscillator_Init(void)
{
    char SFRPAGE_SAVE = SFRPAGE;        //Save Current SFR Page

    SFRPAGE = CONFIG_PAGE;                //SFR page Configurations OR Set SFR Page
    OSCICN = 0x83;                        //Enable Internal Oscillator to run at its maximum frequency 

    while(!(OSCICN & (1 << 6)));        // Wait until--------

    SFRPAGE = SFRPAGE_SAVE;                //restore SFR PAGE    
    return (char)SUCCESS;       //returning SUCCESS
}
void PLL_Init()
{

    unsigned char SFRPAGE_SAVE = SFRPAGE;
    unsigned char ucCount = 0;    

    SFRPAGE    =    LEGACY_PAGE;

    FLSCL    =    (FLRT << 4); // Program the Flash read timing bits,to the appropriate value for the new clock rate, FLCL == 11 ; SYSTEM CLK <100MHz

    SFRPAGE    =    PLL0_PAGE;

    PLL0CN =    (PLLPWR) ;// Enable power to the PLL by setting 1

    PLL0DIV    =    DIVIDENT_1;// Program the PLL0DIV register to produce the divided reference frequency to the PLL

    PLL0FLT    =    PLLLP;// Program the PLLLP3-0 (PLL Loop Filter Control Bits) bits to the appropriate range for the divided frequence range

    //Selection is based on the divided PLL reference clock, 19-30 MHz - 0001 (PLLP):
    
    PLL0MUL    =    4; // Program the PLL0MUL register to the desired clock multiplication factor

    for(ucCount = 0; ucCount < 100 ; ucCount++) //Wait at least 5 µs, to provide a fast frequency lock
    {
    }

    PLL0CN        |=    PLLEN; // Enable the PLL by setting PLLEN (PLL0CN.1) to ‘1’

    while(!(PLL0CN & (1 << PLLLCK))); // Poll PLLLCK (PLL0CN.4) until it changes from ‘0’ to ‘1’.

    CLKSEL = 0x2; // Switch the System Clock source to the PLL using the CLKSEL register.

    SFRPAGE = LEGACY_PAGE;                //load legacy page
    RSTsrc=0x06;                        
    SFRPAGE = SFRPAGE_SAVE;                //restore SFR PAGE

    SFRPAGE    =    SFRPAGE_SAVE;

}

char Port_Initialize()
{
    unsigned char SFRPAGE_SAVE     = SFRPAGE;
    SFRPAGE                         = CONFIG_PAGE;
    SFRPGCN                     = 0x00;

 
    XBR0 = 0x07; //  UART0 TX routed to P0.0, and RX routed to P0.1 , SPI0 SCK, MISO, MOSI, and NSS routed to 4 Port pins , SMBus0 SDA and SCL routed to 2 Port pins.

    XBR2                        = (1 << 6); // Enabling the cross bar Selection

    P0MDOUT                        = 0xE8;
    P0                                     = 0xFF;

    SFRPAGE                        = SFRPAGE_SAVE;

    return (char)SUCCESS;
}

char SPI_Init()
{

    unsigned char SFRPAGE_SAVE = SFRPAGE; // Save the current SFRPAGE

    SFRPAGE   = SPI0_PAGE; // Switch to the necessary SFRPAGE

    SPI0CFG   = 0x00; //0x07 /* Set the Clock Polarity - 0, Clock Phase - 0 */ (Both Master & Slave must be configured to use the same ClkPahse & ClkPolrity)

    SPI0CN    = 0x01;    //Enable SPI

    /* Disable SPI Interrupt */
    EnableSPI_Interrupt(0x00);
    
    SFRPAGE = SFRPAGE_SAVE;

    return (char)SUCCESS;
}

unsigned char EnableSPI_Interrupt(unsigned char in_ucInterruptFlag)
{
    if(in_ucInterruptFlag == 0x00)
    {
        EIE1      &= 0xFE;                        // Disable SPI0 Interrupts
    }

    else
    {
        EIE1      |= 0x01;                        // Enable SPI0 Interrupts
    }
    return (char)SUCCESS;       //returning SUCCESS
}

void SPI_Data_Read(unsigned char *pucData)
{
    unsigned char ucRead_data;

    SPIReadByte(&ucRead_data);
}

void SPIReadByte(unsigned char *pucData)
{

    unsigned char SFRPAGE_SAVE=SFRPAGE;
    unsigned char ucTemp=0;
    unsigned long ulTemp=0;
    unsigned char ucData = 0;

    SFRPAGE   = SPI0_PAGE;

    while(SPI0CFG & 0x80)
    {
        //disable SPI
        SPIEN   = 0x0;
        //Enable SPI
        SPIEN   = 0x1;
    }

    for(ucTemp=0; ucTemp<255;ucTemp++);    //Delay

    /** Read **/
    ucData = SPI0DAT;

//    while (SPIF == 0);
//        SPIF = 0;

    *pucData = ucData;

    SFRPAGE=SFRPAGE_SAVE;
}

Thanks for your kind reply.

The problem is , I haven't set & restore the SFRPAGE  in Power_On_Init() function where I am toggling the P4 Pins. After including the SFRPAGE, now its working fine.

But my doubt is, without this SFRPAGE set & restore P0 to P3 is working ? why not P4 to P7 ??

char Port_Initialize()
{
    unsigned char SFRPAGE_SAVE     = SFRPAGE;
    SFRPAGE                                       = CONFIG_PAGE;
    SFRPGCN                                       = 0x00;
     
    P4MDOUT                        = 0xFF; // P4 pins are  configuring as Output (Push Pull mode).
 are making as Push Pul Output.

    SFRPAGE                        = SFRPAGE_SAVE;

    return (char) SUCCESS;
}

void Power_On_Init()
{
 
    PORT_FOUR_ZERO    = 0;

    PORT_FOUR_ONE      = 0;
    PORT_FOUR_TWO     = 0;
    PORT_FOUR_THREE  = 0;
    PORT_FOUR_FOUR    = 0;

    return;
}

void main()

{
    Port_Initialize();

    Power_On_Init();

}

 

Note : I have included lines related with the Port 4 only . P0 to P3 is working fine.

          PORT_FOUR_ZERO macro defined in corresponding header file (sbit PORT_FOUR_ZERO = P4^0 etc ..).

 

I have enabled the SFR also.

Hi,
I just want to configure the Port 4 Pin as Push Pull output . So that I have configured
P4MDOUT = 0xFF . ( SFR page also selected as CONFIG )
But after making the corresponding pins as low or high . Port pin output state is not latching . Always it's in High state , even I had made it as low . I need to configure any Cross bar register ?Is there anything I have missed out ? Please help me ....