Three Reasons PCI Express (PCIe) is in Portable Devices, Digital Cameras, and Consumer Devices on Blog
PCI Express (PCIe) in Portable Devices and Consumer Devices
Intel first defined and deployed the PCI Express (PCIe) serial computer expansion bus for computing and server applications in the early 2000s. The PCI-SIG has now expanded to over 900 member companies and is getting ready to ratify the 4th official generation of PCIe, expected to be available for industry adoption in 2016 or 2017. The new standard will double data throughput over PCIe’s 3rd generation standard to 16 gigatransfers/second.
The driving technical needs for a high-speed interconnect bus in servers and computing platforms are fairly obvious. Modern systems have gigabytes of high-speed data constantly shuttling from processors to graphics cards and memory inside the platform. This also applies to consumer devices like gaming consoles and remote memory drives. But it’s only in recent years that similar data demands have led to a need for PCIe in portable devices.
There are three important trends that make adding PCIe to low-price consumer devices possible.
In particular, companies that design digital cameras, DSLRs, and video cameras are adopting PCIe Gen1 and Gen2 widely to use their high-speed throughput and low price points.
With 4K video and image sizes nearing 20 megapixels, these features rely on high-speed data transport to clear caches, stream data into memory, and rapidly move images out of the device into external memory. To provide the best possible user experience, PCIe interconnects are used between the image sensor and processor, and again between the processor and 4K codecs. This enhances important features like image capture time, rapid-fire images, and high resolution video (e.g., 4K and slo-mo).
Silicon Labs is at the forefront of supporting consumer companies with PCIe. Our Si5211x PCIe clock family includes very small package Gen1, Gen2, and Gen3 clocks, and is very low power and cost effective. It is already widely adopted in production consumer devices around the world.
Because it supports PCIe Gen1, Gen2 and Gen3 timing requirements, it can be reused as products go from one generation to the next. The devices operate at very low power consumption to conserve battery life, and support down spread spectrum for EMI reduction.
We also provide a free software tool to measure PCIe jitter compliance of PCIe clocks. The tool provides jitter compliance reports for any supplier clocks, and is already supported and used widely by other PCI-SIG members.
Oct 28 2017, 3:57 PM
Measuring PCIe Jitter Compliance to Gen4, Gen3, Gen2, and Gen1 on Blog
Measuring PCIe clock jitter can be a challenging task. Most differential clock signals are specified across a phase jitter filter mask of 12kHz-20MHz, however PCIe differential signals are specified and measured using a different set of complex filter masks. Further, each PCIe generation specification presents a different set of masks to measure PCIe clock jitter. To make things just a little more difficult, most oscilloscope manufacturers do not include the PCIe masks for measuring PCIe clock jitter, requiring designers to purchase costly add-on packages.
To make this whole process easier, Silicon Labs just completed and released a new, free software tool that measures PCIe clock jitter from any supplier using common oscilloscope waveform files. The tool is proven and approved by other PCI-SIG members, and provides compliance data and a report for any PCIe clock source on the market.
As all PCIe clocking suppliers know, it is a common customer request to have multiple sources for the PCIe timing solutions. This free tool also helps to ensure the complementary timing solutions provide similar performance, so if they are swapped out, the overall system performance doesn’t change unpredictably.
We have provided a few examples of our own PCIe clock generators’ compliance reports below. As you will see, the Silicon Labs PCIe clocks provide PCIe Gen4/3/2/1 compliance with better performance than the maximum PCIe timing specifications. This allows for some degree of design error while still meeting the PCIe clocking requirements. This is important in the complex designs using PCIe today, where even a small error can reduce data throughput and perceived performance of the whole system as a result.
We also just consolidated all our PCIe application notes, whitepapers, the free PCIe jitter measurement software, and videos in a single page on our website – The PCIe Learning Center.
For example, some of our solutions use Push/Pull outputs versus Constant Current outputs. As a result reduce power consumption by over 50% and BOM count by over 75%. We have built special boards and described the PCIe output performance in AN871: Alternative Output Terminations and AN951: Driving Long Output Traces to demonstrate and explain how this innovative, power efficient design can drive long trace lengths for complex designs while saving significant energy—an important consideration for today’s power-hungry designs.
We also provide a detailed examination of the new PCIe Gen4 jitter requirements in AN946: PCI Express (PCIe) 4.0 Jitter Requirements.
I hope you’ll find the new PCIe learning center and free PCIe jitter measurement tool valuable.
Oct 28 2017, 3:55 PM
What is PCIe Gen4, and how is it different than PCIe Gen1/2/3? on Blog
As a long-time Timing engineer and PCIe advocate, I am happy to share that Silicon Labs recently introduced a new family of PCIe Gen4 compliant clocks and buffers to our existing portfolio of leading PCIe solutions.
PCIe Gen4 is a new standardized data transfer bus that will double the data transfer rate per lane of the prior Gen3 revision from 8.0 GT/s (gigatransfers/second) to 16.0 GT/s. This means that a single PCIe Gen4 interconnection will allow data rate transfers of up to 2GB/s (gigabytes/second), and a full 16 slot PCIe Gen4 interconnection for graphics cards and high-end solid state drives will allow data transfer rates of up to 32GB/s.
This increased data transfer rate will facilitate the demanding data transfer rates of new servers and data farms as cloud storage, services, and software become more and more prevalent. It will also allow mobile devices to transfer information super quickly, thus reducing power consumption during downloads or data synchronization activities.
The PCI-SIG is comprised of over 900 companies and has been developing the Gen4 revision since 2011. The standards committee has a rev 0.7 spec available as of December 2015, and the final 1.0 specification will likely be released in 2016.
The PCIe clocking and buffer requirements are expected to remain unchanged between 0.7 and 1.0; however, one of the options the PCI-SIG is considering is to remove the clocking requirements from the 1.0 specification altogether. This would make clock compliance testing incumbent solely on adopters, who would then measure performance and compliance by measuring the data stream. This would lead to a more challenging debug effort since a key variable would no longer be defined.
While this would give flexibility in budgeting jitter margin between the clock source and transceiver, it would allow inferior clocking solutions to claim PCIe compatibility without any accountability. This would create extra work for users to qualify clock sources, especially when trying to identify multiple sources of compatible clocks and transceivers.
To help customers who are adopting PCIe, we developed the free PCIe Clock Jitter Tool to measure the output jitter of PCIe clocks. This free tool works with any PCIe clock regardless of supplier. It can be found at the Silicon Labs PCIe Learning Center where we have posted multiple PCIe application notes and information on selecting PCIe clocks and buffers.
I hope you will check out the new PCIe learning center, and will find the new PCIe jitter measurement tool useful. Please let us know if you have any suggestions.
Oct 28 2017, 3:55 PM