Introduction

In this follow-up post, The Case of the Noisy Source Clock Tree Part 2, I will discuss in more detail exactly how to calculate the total jitter for a noisy source clock tree that includes a jitter attenuator. I will also provide a measurement and spreadsheet example.

Recap

In Part 1, I first discussed the low jitter source canonical clock tree, how to calculate the total jitter by Root Sum Square, and reviewed the terms jitter transfer, jitter generation, and additive jitter. I then moved on to the noisy source clock tree, the motivation for adding jitter attenuation, and introduced how to calculate its total jitter.

As I mentioned last time, following the clock signal from the source through the clock tree components to the sink or destination is best viewed as a system that processes phase noise. That is, if we know the phase noise characteristics of each clock tree component, we should be able to estimate the end clock phase noise and its phase jitter over a particular jitter bandwidth.

By best I mean that this approach is more universal and accurate. It can be applied to all types of clock trees, with or without noisy sources and jitter attenuators.

The Basic Idea

The general approach is illustrated below. Every clock tree can be regarded as a cascade of phase noise processing elements each of which, in the most general sense, can be modeled as the Root Sum Square or RSS of the Jitter Generation (JGEN) phase noise in contribution with the Jitter Transfer Function (JTF) applied to the scaled input clock phase noise.

Scaling is required so that the components contributing to the RSS are all at the same carrier frequency. The details will be made clearer in the example that follows.

The ith element above illustrates the general clock tree component model. All the contributions shown apply in the case of a jitter attenuator which also multiplies or divides the input clock. However, in practice, not all aspects of the general model apply, or are readily available, for every clock tree component:

1. The independent clock source such as an XO at Element “1”, the root of the clock tree, has no input clock so the JTF branch is zeroed out. It can be modeled simply as JGEN, i.e. the source’s output clock phase noise.
2. The typical clock generator has a wide bandwidth so the JTF contribution is negligible and it too is modeled simply as JGEN.
3. The clock buffer has no PLL so JGEN is not applicable. Unfortunately, a JTF is usually not available. We typically have to rely on additive jitter specified over a particular bandwidth or do further characterization.

A Practical Measurement Example

Consider the following simplified block diagram. I used an Arbitrary Waveform Generator or AWG as my noisy 50 MHz input clock source and followed it with an Si5345 evaluation board. The Si5345 does both jitter attenuation and clock multiplication as is the common practical case. I then followed the jitter attenuator (JA) with an Si53301 clock buffer evaluation board. The output clocks for both the jitter attenuator and clock buffer are 156.25 MHz.

No baluns or limiters were used. Just straightforward single-ended connections to and from test equipment and differential connections between the jitter attenuator and clock buffer. The unmeasured output clock polarity was terminated on the clock buffer EVB.

Calculating Phase Jitter

In the work that follows, we often want to calculate RMS phase jitter, i.e. integrated phase noise over a select frequency range, from a dataset of phase noise L(f) (dBc/Hz) versus offset frequency f (Hz). For the purpose of this exercise, we ignore spurs though they can certainly be included.

The general procedure is as follows.

1. Convert SSB phase noise data L(f) from dBc/Hz to W/Hz.                                                             
2. "Brickwall" filter the data over the selected jitter filter bandwidth. In this example, we take 12 kHz to 20 MHz. (Sloped filters can be used too but not in these particular spreadsheets.)                                      
3. Over the jitter filter bandwidth, take the average of the current and previous spot phase noise measurements (W/Hz) multiplied by the difference in offset frequencies (Hz).                                           
4. Sum all these jitter power contributions.                                                                   
5. Double to account for DSB or Double Sideband and then convert to UI or Unit Intervals.                       
6. Finally, convert from UI to time domain units, typically fs.             

As will be seen, the worksheets that use this technique calculate values very close to what the phase noise instrument reports.

Measurement Steps

I have attached a spreadsheet, PhaseJitterCalcsClockTreeWithoutSpurs.xlsx, that records the results and compares them to lab measurements in the form of Agilent E5052B screen caps. There are 9 total measurements steps listed below in worksheet order as follows with additional details. The convention on the calculations worksheets is that input data are in yellow colored cells.

1. 50 MHz AWG Meas Data - Measure the AWG’s 50 MHz phase noise. This is the clock phase noise that will be input to the jitter attenuator. This worksheet imports the CSV file containing the measured phase noise for an Arbitrary Waveform Generator (AWG) operating at nominal 0 dBm and 50 MHz.
2. 50 MHz AWG Calcs - Calculate the AWG’s 50 MHz phase jitter based on the measured phase noise data using the procedure described earlier. In this context, the term “phase jitter” always refers to the RMS quantity based on integrating phase noise over the 12 kHz – 20 MHz offset frequency range. The calculated result is 7917 fs or 7.7917 ps which is noisy indeed. This result is accurate to 0.1% compared to the figure reported by the Agilent E5052B screen cap.
3. 50 MHz Sig Gen Meas Data - Measure the signal generator’s 50 MHz phase noise. This worksheet imports the CSV file containing the measured phase noise for a signal generator also operating at nominal 0 dBm and 50 MHz.

Note: This is the clock phase noise that will be input to the jitter attenuator (JA) to estimate its Jitter Generation (JGEN) at the output frequency. It was presumed, based on previous experience, that the sig gen’s performance would be better than the AWG’s and so would be a good candidate for this role. However, this had to be confirmed.

4. 50 MHz Sig Gen Calcs - Calculate the sig gen’s 50 MHz phase jitter. The calculated result is 785 fs, accurate to 0.02% compared to the figure reported by the Agilent E5052B.  
5. 50 MHz AWG vs Sig Gen Plots - Here I compare the AWG versus the signal generator phase noise, both operating at 50 MHz. Generally speaking the sig gen’s phase noise is close to, or better than, that of the AWG’s performance. The previous worksheets’ calculations showed that the signal generator was roughly an order of magnitude better than the AWG in terms of phase jitter. Given this confirmation, it is reasonable to select the sig gen to be the low noise source for the subsequently estimated JGEN.

Note: It may also be expedient to operate a jitter attenuator in Free Run mode and use its output clock phase noise as a stand-in for JGEN. It does not account for all noise sources but can often get within 5% for typical jitter bandwidths. However, it will not be as accurate at low offset frequencies.

6. JGEN 156.25 MHz Meas Data - This worksheet imports the CSV file containing the JA’s 156.25 MHz output clock measured phase noise where the low noise RF signal generator supplies the 50 MHz input clock. This data is used to the estimate the JA’s JGEN.
7. JGEN 156.25 MHz Calcs - Calculates the JA’s JGEN phase jitter. The calculated result is 83.5 fs, accurate to 0.03% compared to the figure reported by the Agilent E5052B.
8. Clock Tree Calcs - This is the clock tree calculations worksheet that puts everything together. Inspecting the columns going from left to right you can see the following operations:

• Scale the input clock phase noise with reference to the output clock carrier frequency.
• Apply jitter attenuation. Here we assume a low pass filter response with 40 dB /dec attenuation starting at the loop BW frequency 100 Hz. This is a simplified version, accurate well beyond the corner frequency. (The more accurate the JTF, the better the results.)
• Bring in the JGEN data from worksheet “7. JGEN 156.25 MHz Meas Calcs”.
• RSS the contributions from the JGEN phase noise plus the scaled jitter attenuated phase noise.
• Calculate the phase jitter for the JA’s output clock.
• Finally, calculate the phase jitter for the clock buffer’s output clock. There is no JTF for this buffer but there is a specified typical spec of 145 fs additive phase jitter, 12 kHz – 20 MHz.

Two different E5052B screen caps are copied on to this last calculations worksheet, one for the JA output clock, and one for the buffer output clock.

9. Clock Tree Plots - All of the relevant input, interim, and output curves for the jitter attenuator are plotted here.

Overall Results

So how did it go? It went reasonably well with a caveat at the end.

The JA output clock phase jitter was calculated to be 83.47 fs which was 0.9% lower than the measured 84.19 fs. The shape of the measured phase noise plot looks close to the expected plot except close in.

The buffer output clock phase noise was calculated to be 167.31 fs which was -5.2 % lower than measured, based on using the datasheet typical value for additive jitter, 12 kHz – 20 MHz. We don’t simply see +1 or +2 dB added everywhere to the JA output clock phase noise. Rather, the shape of the measured phase noise plot showed more phase noise at far offset frequencies, where the “floor” rose from about -162 to -152 dBc/Hz.

Bottom line: These results are good from a phase jitter point of view. However, it appears that a buffer JTF would be needed to better predict the end phase noise plot.

Conclusion

I hope you have enjoyed this Timing 101 article. This is the last post for 2018. Happy Holidays and Happy New Year to you all! I look forward to exploring more topics with you in 2019.

As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 101 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,

Kevin

Introduction

In this follow-up post, The Case of the Noisy Source Clock Tree Part 2, I will discuss in more detail exactly how to calculate the total jitter for a noisy source clock tree that includes a jitter attenuator. I will also provide a measurement and spreadsheet example.

Recap

In Part 1, I first discussed the low jitter source canonical clock tree, how to calculate the total jitter by Root Sum Square, and reviewed the terms jitter transfer, jitter generation, and additive jitter. I then moved on to the noisy source clock tree, the motivation for adding jitter attenuation, and introduced how to calculate its total jitter.

As I mentioned last time, following the clock signal from the source through the clock tree components to the sink or destination is best viewed as a system that processes phase noise. That is, if we know the phase noise characteristics of each clock tree component, we should be able to estimate the end clock phase noise and its phase jitter over a particular jitter bandwidth.

By best I mean that this approach is more universal and accurate. It can be applied to all types of clock trees, with or without noisy sources and jitter attenuators.

The Basic Idea

The general approach is illustrated below. Every clock tree can be regarded as a cascade of phase noise processing elements each of which, in the most general sense, can be modeled as the Root Sum Square or RSS of the Jitter Generation (JGEN) phase noise in contribution with the Jitter Transfer Function (JTF) applied to the scaled input clock phase noise.

Scaling is required so that the components contributing to the RSS are all at the same carrier frequency. The details will be made clearer in the example that follows.

The ith element above illustrates the general clock tree component model. All the contributions shown apply in the case of a jitter attenuator which also multiplies or divides the input clock. However, in practice, not all aspects of the general model apply, or are readily available, for every clock tree component:

1. The independent clock source such as an XO at Element “1”, the root of the clock tree, has no input clock so the JTF branch is zeroed out. It can be modeled simply as JGEN, i.e. the source’s output clock phase noise.
2. The typical clock generator has a wide bandwidth so the JTF contribution is negligible and it too is modeled simply as JGEN.
3. The clock buffer has no PLL so JGEN is not applicable. Unfortunately, a JTF is usually not available. We typically have to rely on additive jitter specified over a particular bandwidth or do further characterization.

A Practical Measurement Example

Consider the following simplified block diagram. I used an Arbitrary Waveform Generator or AWG as my noisy 50 MHz input clock source and followed it with an Si5345 evaluation board. The Si5345 does both jitter attenuation and clock multiplication as is the common practical case. I then followed the jitter attenuator (JA) with an Si53301 clock buffer evaluation board. The output clocks for both the jitter attenuator and clock buffer are 156.25 MHz.

No baluns or limiters were used. Just straightforward single-ended connections to and from test equipment and differential connections between the jitter attenuator and clock buffer. The unmeasured output clock polarity was terminated on the clock buffer EVB.

Calculating Phase Jitter

In the work that follows, we often want to calculate RMS phase jitter, i.e. integrated phase noise over a select frequency range, from a dataset of phase noise L(f) (dBc/Hz) versus offset frequency f (Hz). For the purpose of this exercise, we ignore spurs though they can certainly be included.

The general procedure is as follows.

1. Convert SSB phase noise data L(f) from dBc/Hz to W/Hz.                                                             
2. "Brickwall" filter the data over the selected jitter filter bandwidth. In this example, we take 12 kHz to 20 MHz. (Sloped filters can be used too but not in these particular spreadsheets.)                                      
3. Over the jitter filter bandwidth, take the average of the current and previous spot phase noise measurements (W/Hz) multiplied by the difference in offset frequencies (Hz).                                           
4. Sum all these jitter power contributions.                                                                   
5. Double to account for DSB or Double Sideband and then convert to UI or Unit Intervals.                       
6. Finally, convert from UI to time domain units, typically fs.             

As will be seen, the worksheets that use this technique calculate values very close to what the phase noise instrument reports.

Measurement Steps

I have attached a spreadsheet, PhaseJitterCalcsClockTreeWithoutSpurs.xlsx, that records the results and compares them to lab measurements in the form of Agilent E5052B screen caps. There are 9 total measurements steps listed below in worksheet order as follows with additional details. The convention on the calculations worksheets is that input data are in yellow colored cells.

1. 50 MHz AWG Meas Data - Measure the AWG’s 50 MHz phase noise. This is the clock phase noise that will be input to the jitter attenuator. This worksheet imports the CSV file containing the measured phase noise for an Arbitrary Waveform Generator (AWG) operating at nominal 0 dBm and 50 MHz.
2. 50 MHz AWG Calcs - Calculate the AWG’s 50 MHz phase jitter based on the measured phase noise data using the procedure described earlier. In this context, the term “phase jitter” always refers to the RMS quantity based on integrating phase noise over the 12 kHz – 20 MHz offset frequency range. The calculated result is 7917 fs or 7.7917 ps which is noisy indeed. This result is accurate to 0.1% compared to the figure reported by the Agilent E5052B screen cap.
3. 50 MHz Sig Gen Meas Data - Measure the signal generator’s 50 MHz phase noise. This worksheet imports the CSV file containing the measured phase noise for a signal generator also operating at nominal 0 dBm and 50 MHz.

Note: This is the clock phase noise that will be input to the jitter attenuator (JA) to estimate its Jitter Generation (JGEN) at the output frequency. It was presumed, based on previous experience, that the sig gen’s performance would be better than the AWG’s and so would be a good candidate for this role. However, this had to be confirmed.

4. 50 MHz Sig Gen Calcs - Calculate the sig gen’s 50 MHz phase jitter. The calculated result is 785 fs, accurate to 0.02% compared to the figure reported by the Agilent E5052B.  
5. 50 MHz AWG vs Sig Gen Plots - Here I compare the AWG versus the signal generator phase noise, both operating at 50 MHz. Generally speaking the sig gen’s phase noise is close to, or better than, that of the AWG’s performance. The previous worksheets’ calculations showed that the signal generator was roughly an order of magnitude better than the AWG in terms of phase jitter. Given this confirmation, it is reasonable to select the sig gen to be the low noise source for the subsequently estimated JGEN.

Note: It may also be expedient to operate a jitter attenuator in Free Run mode and use its output clock phase noise as a stand-in for JGEN. It does not account for all noise sources but can often get within 5% for typical jitter bandwidths. However, it will not be as accurate at low offset frequencies.

6. JGEN 156.25 MHz Meas Data - This worksheet imports the CSV file containing the JA’s 156.25 MHz output clock measured phase noise where the low noise RF signal generator supplies the 50 MHz input clock. This data is used to the estimate the JA’s JGEN.
7. JGEN 156.25 MHz Calcs - Calculates the JA’s JGEN phase jitter. The calculated result is 83.5 fs, accurate to 0.03% compared to the figure reported by the Agilent E5052B.
8. Clock Tree Calcs - This is the clock tree calculations worksheet that puts everything together. Inspecting the columns going from left to right you can see the following operations:

• Scale the input clock phase noise with reference to the output clock carrier frequency.
• Apply jitter attenuation. Here we assume a low pass filter response with 40 dB /dec attenuation starting at the loop BW frequency 100 Hz. This is a simplified version, accurate well beyond the corner frequency. (The more accurate the JTF, the better the results.)
• Bring in the JGEN data from worksheet “7. JGEN 156.25 MHz Meas Calcs”.
• RSS the contributions from the JGEN phase noise plus the scaled jitter attenuated phase noise.
• Calculate the phase jitter for the JA’s output clock.
• Finally, calculate the phase jitter for the clock buffer’s output clock. There is no JTF for this buffer but there is a specified typical spec of 145 fs additive phase jitter, 12 kHz – 20 MHz.

Two different E5052B screen caps are copied on to this last calculations worksheet, one for the JA output clock, and one for the buffer output clock.

9. Clock Tree Plots - All of the relevant input, interim, and output curves for the jitter attenuator are plotted here.

Overall Results

So how did it go? It went reasonably well with a caveat at the end.

The JA output clock phase jitter was calculated to be 83.47 fs which was 0.9% lower than the measured 84.19 fs. The shape of the measured phase noise plot looks close to the expected plot except close in.

The buffer output clock phase noise was calculated to be 167.31 fs which was -5.2 % lower than measured, based on using the datasheet typical value for additive jitter, 12 kHz – 20 MHz. We don’t simply see +1 or +2 dB added everywhere to the JA output clock phase noise. Rather, the shape of the measured phase noise plot showed more phase noise at far offset frequencies, where the “floor” rose from about -162 to -152 dBc/Hz.

Bottom line: These results are good from a phase jitter point of view. However, it appears that a buffer JTF would be needed to better predict the end phase noise plot.

Conclusion

I hope you have enjoyed this Timing 101 article. This is the last post for 2018. Happy Holidays and Happy New Year to you all! I look forward to exploring more topics with you in 2019.

As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 101 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,

Kevin

Introduction

In this follow-up post, The Case of the Noisy Source Clock Tree Part 2, I will discuss in more detail exactly how to calculate the total jitter for a noisy source clock tree that includes a jitter attenuator. I will also provide a measurement and spreadsheet example.

Recap

In Part 1, I first discussed the low jitter source canonical clock tree, how to calculate the total jitter by Root Sum Square, and reviewed the terms jitter transfer, jitter generation, and additive jitter. I then moved on to the noisy source clock tree, the motivation for adding jitter attenuation, and introduced how to calculate its total jitter.

As I mentioned last time, following the clock signal from the source through the clock tree components to the sink or destination is best viewed as a system that processes phase noise. That is, if we know the phase noise characteristics of each clock tree component, we should be able to estimate the end clock phase noise and its phase jitter over a particular jitter bandwidth.

By best I mean that this approach is more universal and accurate. It can be applied to all types of clock trees, with or without noisy sources and jitter attenuators.

The Basic Idea

The general approach is illustrated below. Every clock tree can be regarded as a cascade of phase noise processing elements each of which, in the most general sense, can be modeled as the Root Sum Square or RSS of the Jitter Generation (JGEN) phase noise in contribution with the Jitter Transfer Function (JTF) applied to the scaled input clock phase noise.

Scaling is required so that the components contributing to the RSS are all at the same carrier frequency. The details will be made clearer in the example that follows.

The ith element above illustrates the general clock tree component model. All the contributions shown apply in the case of a jitter attenuator which also multiplies or divides the input clock. However, in practice, not all aspects of the general model apply, or are readily available, for every clock tree component:

1. The independent clock source such as an XO at Element “1”, the root of the clock tree, has no input clock so the JTF branch is zeroed out. It can be modeled simply as JGEN, i.e. the source’s output clock phase noise.
2. The typical clock generator has a wide bandwidth so the JTF contribution is negligible and it too is modeled simply as JGEN.
3. The clock buffer has no PLL so JGEN is not applicable. Unfortunately, a JTF is usually not available. We typically have to rely on additive jitter specified over a particular bandwidth or do further characterization.

A Practical Measurement Example

Consider the following simplified block diagram. I used an Arbitrary Waveform Generator or AWG as my noisy 50 MHz input clock source and followed it with an Si5345 evaluation board. The Si5345 does both jitter attenuation and clock multiplication as is the common practical case. I then followed the jitter attenuator (JA) with an Si53301 clock buffer evaluation board. The output clocks for both the jitter attenuator and clock buffer are 156.25 MHz.

No baluns or limiters were used. Just straightforward single-ended connections to and from test equipment and differential connections between the jitter attenuator and clock buffer. The unmeasured output clock polarity was terminated on the clock buffer EVB.

Calculating Phase Jitter

In the work that follows, we often want to calculate RMS phase jitter, i.e. integrated phase noise over a select frequency range, from a dataset of phase noise L(f) (dBc/Hz) versus offset frequency f (Hz). For the purpose of this exercise, we ignore spurs though they can certainly be included.

The general procedure is as follows.

1. Convert SSB phase noise data L(f) from dBc/Hz to W/Hz.                                                             
2. "Brickwall" filter the data over the selected jitter filter bandwidth. In this example, we take 12 kHz to 20 MHz. (Sloped filters can be used too but not in these particular spreadsheets.)                                      
3. Over the jitter filter bandwidth, take the average of the current and previous spot phase noise measurements (W/Hz) multiplied by the difference in offset frequencies (Hz).                                           
4. Sum all these jitter power contributions.                                                                   
5. Double to account for DSB or Double Sideband and then convert to UI or Unit Intervals.                       
6. Finally, convert from UI to time domain units, typically fs.             

As will be seen, the worksheets that use this technique calculate values very close to what the phase noise instrument reports.

Measurement Steps

I have attached a spreadsheet, PhaseJitterCalcsClockTreeWithoutSpurs.xlsx, that records the results and compares them to lab measurements in the form of Agilent E5052B screen caps. There are 9 total measurements steps listed below in worksheet order as follows with additional details. The convention on the calculations worksheets is that input data are in yellow colored cells.

1. 50 MHz AWG Meas Data - Measure the AWG’s 50 MHz phase noise. This is the clock phase noise that will be input to the jitter attenuator. This worksheet imports the CSV file containing the measured phase noise for an Arbitrary Waveform Generator (AWG) operating at nominal 0 dBm and 50 MHz.
2. 50 MHz AWG Calcs - Calculate the AWG’s 50 MHz phase jitter based on the measured phase noise data using the procedure described earlier. In this context, the term “phase jitter” always refers to the RMS quantity based on integrating phase noise over the 12 kHz – 20 MHz offset frequency range. The calculated result is 7917 fs or 7.7917 ps which is noisy indeed. This result is accurate to 0.1% compared to the figure reported by the Agilent E5052B screen cap.
3. 50 MHz Sig Gen Meas Data - Measure the signal generator’s 50 MHz phase noise. This worksheet imports the CSV file containing the measured phase noise for a signal generator also operating at nominal 0 dBm and 50 MHz.

Note: This is the clock phase noise that will be input to the jitter attenuator (JA) to estimate its Jitter Generation (JGEN) at the output frequency. It was presumed, based on previous experience, that the sig gen’s performance would be better than the AWG’s and so would be a good candidate for this role. However, this had to be confirmed.

1. 50 MHz Sig Gen Calcs - Calculate the sig gen’s 50 MHz phase jitter. The calculated result is 785 fs, accurate to 0.02% compared to the figure reported by the Agilent E5052B.  
2. 50 MHz AWG vs Sig Gen Plots - Here I compare the AWG versus the signal generator phase noise, both operating at 50 MHz. Generally speaking the sig gen’s phase noise is close to, or better than, that of the AWG’s performance. The previous worksheets’ calculations showed that the signal generator was roughly an order of magnitude better than the AWG in terms of phase jitter. Given this confirmation, it is reasonable to select the sig gen to be the low noise source for the subsequently estimated JGEN.

Note: It may also be expedient to operate a jitter attenuator in Free Run mode and use its output clock phase noise as a stand-in for JGEN. It does not account for all noise sources but can often get within 5% for typical jitter bandwidths. However, it will not be as accurate at low offset frequencies.

1. JGEN 156.25 MHz Meas Data - This worksheet imports the CSV file containing the JA’s 156.25 MHz output clock measured phase noise where the low noise RF signal generator supplies the 50 MHz input clock. This data is used to the estimate the JA’s JGEN.
2. JGEN 156.25 MHz Calcs - Calculates the JA’s JGEN phase jitter. The calculated result is 83.5 fs, accurate to 0.03% compared to the figure reported by the Agilent E5052B.
3. Clock Tree Calcs - This is the clock tree calculations worksheet that puts everything together. Inspecting the columns going from left to right you can see the following operations:

• Scale the input clock phase noise with reference to the output clock carrier frequency.
• Apply jitter attenuation. Here we assume a low pass filter response with 40 dB /dec attenuation starting at the loop BW frequency 100 Hz. This is a simplified version, accurate well beyond the corner frequency. (The more accurate the JTF, the better the results.)
• Bring in the JGEN data from worksheet “7. JGEN 156.25 MHz Meas Calcs”.
• RSS the contributions from the JGEN phase noise plus the scaled jitter attenuated phase noise.
• Calculate the phase jitter for the JA’s output clock.
• Finally, calculate the phase jitter for the clock buffer’s output clock. There is no JTF for this buffer but there is a specified typical spec of 145 fs additive phase jitter, 12 kHz – 20 MHz.

Two different E5052B screen caps are copied on to this last calculations worksheet, one for the JA output clock, and one for the buffer output clock.

1. Clock Tree Plots - All of the relevant input, interim, and output curves for the jitter attenuator are plotted here.

Overall Results

So how did it go? It went reasonably well with a caveat at the end.

The JA output clock phase jitter was calculated to be 83.47 fs which was 0.9% lower than the measured 84.19 fs. The shape of the measured phase noise plot looks close to the expected plot except close in.

The buffer output clock phase noise was calculated to be 167.31 fs which was -5.2 % lower than measured, based on using the datasheet typical value for additive jitter, 12 kHz – 20 MHz. We don’t simply see +1 or +2 dB added everywhere to the JA output clock phase noise. Rather, the shape of the measured phase noise plot showed more phase noise at far offset frequencies, where the “floor” rose from about -162 to -152 dBc/Hz.

Bottom line: These results are good from a phase jitter point of view. However, it appears that a buffer JTF would be needed to better predict the end phase noise plot.

Conclusion

I hope you have enjoyed this Timing 101 article. This is the last post for 2018. Happy Holidays and Happy New Year to you all! I look forward to exploring more topics with you in 2019.

As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 101 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,

Kevin

We have seen a support program bundled w/ CBPro flagged by some virus packages in the past. We have been able to get this white listed with the Virus vendors. The program was hex2boot.exe. This is a converted Python script to generate a hex file for certain supported devices.

Could you provide more detail on what Avira reported? 

I also used V2.28.1 but have not found any reported virus with it. Would you like to try the latest version 2.29 to see if the alarm is still there?

https://www.silabs.com/documents/login/software/ClockBuilder-Pro-Installer.zip

I also used V2.28.1 but have not found any reported virus with it. Would you like to try the latest version 2.29 to see if the alarm is still there?

https://www.silabs.com/documents/login/software/ClockBuilder-Pro-Installer.zip

Introduction

In this post, The Case of the Noisy Source Clock Tree Part 1, we will go a step beyond the prototypical or “canonical” clock tree. I will discuss the motivation for adding a jitter attenuator and its impact on clock tree jitter estimation. So let’s get started.

The Canonical Clock Tree

The board level clock tree or clock distribution network, for say a data center application, is typically depicted with a crystal or low jitter XO (crystal oscillator) connected to a clock generator followed by one or more buffers, something like the following. This is what I refer to as the canonical clock tree:

The root or source of the clock tree in this example is a low jitter XO which determines the frequency stability of the clock tree overall. The clock generator then scales the input frequency from the XO to several different (usually higher) output frequencies. Finally, the clock buffer takes one of these output frequencies and yields multiple output clocks with the same frequency. The colored arrows in the figure are meant to suggest different clock frequencies.

We can estimate the total or end clock phase jitter of the canonical clock tree by applying the RSS or Root Sum of the Squares of the individual contributions. (This is the same summation in quadrature math used in cascaded statistical analysis of mechanical tolerances and other errors or uncertainties.) 

For the example above, we can estimate the total RMS phase jitter as

Note that several prerequisites must hold true for this calculation to be valid:

1. The phase jitter contributions should be uncorrelated.
2. Each phase jitter contribution must be integrated over the same jitter bandwidth, e.g. 12 kHz to 20 MHz.
3. Finally, every device in the clock tree is wideband with respect to the clocks involved.

Jitter Transfer versus Jitter Generation versus Additive Jitter

The last statement above means that the bandwidth of the clock generator is wide enough compared to the input clock phase noise that we need not consider the clock generator’s jitter transfer. You may recall that jitter transfer or jitter attenuation measures output clock jitter versus input clock jitter. This is often written as the Jitter Transfer Function or JTF.  A PLL’s JTF acts as a low pass filter to input jitter and is a function of PLL bandwidth.

Jitter generation refers to the intrinsic jitter of a device. In the case of a clock generator, it is a measure of the output jitter when an ideal (no jitter) input clock is applied.  A PLL-based clock device, even with a perfect input clock applied, still has PFD (Phase Frequency Detector) path noise and an intrinsic phase noise source, the VCO. Thus the need for a jitter generation term. 

By contrast, clock buffers consisting only of amplifiers and perhaps dividers will always contribute additional noise to any input clock. Hence the use of the term additive jitter.

The Noisy Source Case

The example canonical clock tree above assumes a low noise clock as in a typical application. However not all clock trees have a low noise clock source.

What categorizes a source clock as relatively low or high noise?  Let’s ignore the follow-on clock buffer for now and just compare the XO’s jitter generation versus the clock generator’s jitter generation. If they were exactly the same, the total jitter would increase by a factor of SQRT(2) or 41% which is substantial. If we choose the usual engineering convention of a 10% increase denoting significance, then we can back out that the XO’s phase jitter should be < 46% of the clock generator’s phase jitter. In other words, the source jitter must approach approximately half the clock generator’s jitter to significantly increase the output clock jitter.

A noisy (jittery) clock could be a recovered clock from serial data or derived from an FPGA. Perhaps the board itself is introducing power supply noise in to the XO. Such a clock tree then behaves as indicated in the figure below. The waveforms are shown thicker here than in the previous figure to suggest higher jitter.

We can still apply the RSS estimate even for a noisy source clock. However, often the resulting jitter will be too high for a typical clock distribution application. So what is our recourse?

Jitter Attenuator to the Rescue

In such applications, we need to add a jitter attenuator to clean up the source clock noise and improve the clock tree jitter performance. The figure below illustrates the basic idea where we have inserted a jitter attenuator between the noisy FPGA-derived source clock and the clock generator. Post jitter attenuator, the rest of the clock tree now looks like the canonical case.  Note that in practical applications, a single device often performs both the jitter attenuator and clock generator scaling functions.

Like the clock generator, the jitter attenuator is a PLL-based device whose JTF acts as a low pass filter to input jitter. However, unlike the clock generator, the jitter attenuator is a relatively narrow bandwidth device versus the input clock phase noise. This violates one of the prerequisites for using the RSS estimate method. So, what is the best approach to calculate the expected phase jitter of the jitter attenuator output clock, and by extension the total or end clock jitter?   

Clock Tree as a Phase Noise Processing System

In engineering, we usually analyze and measure the performance of systems in the frequency domain. Clock distribution networks aka clock trees are no different. The primary attribute of a clock is its frequency and the RMS phase jitter quantities are integrated from phase noise data. It should come as no surprise then that the better and more rigorous way to analyze clock trees generally is in the frequency domain.

In fact, following the clock signal from the source through jitter attenuators, clock generators or multipliers, and buffers, to the sink or destination is best viewed as a system that processes phase noise (this is an example of “one man’s noise is another man’s signal”).

The application of jitter attenuators in particular can really only be well understood by working in the frequency domain. The JTF can be modeled simply by the PLL bandwidth and expected attenuation in the jitter bandwidth of interest. At each phase noise offset frequency f we calculate the output clock phase noise in terms of the input clock phase noise, shaped by the JTF, and added in quadrature to the jitter generation phase noise contribution. We can then check to see if the resulting integrated phase jitter meets the required jitter performance.

I will discuss in more detail exactly how to do this and provide a measurement and spreadsheet example in the next post, The Case of the Noisy Source Clock Tree Part 2.

Conclusion

I hope you have enjoyed this Timing 101 article and will look forward to the follow-up.

As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 101 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,

Kevin

Introduction

In this month’s post, I will review a basic, but sometimes overlooked, best practice necessary for making proper output clock measurements. 

Those of you familiar with our clock IC evaluation boards know that we generally AC-couple our input and output clocks and provide separate SMA RF connectors for each polarity of the differential clock signal.  This is the most flexible approach in terms of being able to immediately connect output clocks to single-ended 50 Ω inputs on test equipment such as frequency counters, oscilloscopes, phase noise analyzers, spectrum analyzers, etc. The AC-coupling capacitors keep us from attempting to impose a DC bias on test equipment inputs and vice-versa. 

Here’s the best practice rule:  Both polarities of differential output buffers should be terminated when making measurements. This include the polarity that is not being measured.  What are the consequences for not doing this?  That is the subject of this article, The Case of the Half-terminated Differential Output Clock.  

Example Phase Noise Measurement

First, let’s work in the frequency domain.  Consider the phase noise plot below. It is from OUT0 of an Si5345 evaluation board for these 2 cases annotated in the screen capture.

1. OUT0B is routed to a 50 Ω oscilloscope input. This is the properly (fully) terminated case.   
2. OUT0B is routed to a 1 MΩ oscilloscope input. This is the half-terminated case.

The output format is 2.5V LVDS AC-coupled with the nominal frequency set to 161.1328125 MHz based on the current CBPro sample plan.  The board is actually in Free Run mode just to minimize the bench set-up.

In the first case, the 12 kHz to 20 MHz RMS phase jitter measured 89.512 fs.  This curve was saved in memory.  In the second case, the 12 kHz to 20 MHz RMS phase jitter increased to 124.16 fs. That’s not bad but the relative increase is about 39%. That is a significant impact.

Example Oscilloscope Measurements

Next we’ll work in the time domain.  Consider the oscilloscope plots below. The top trace is OUT0 assigned to channel 2, OUT0B is assigned to channel 3, and the common mode (CM) voltage is computed as f1. Note that since we are on the far side of the AC-coupling capacitor, we aren’t measuring the DC value but rather the noise represented by the average value of AC-coupled OUT0 and OUT0B.  (The difference in scales here is to accommodate the half-terminated case and is not relevant to the calculation.)

In this first screen capture, both oscilloscope inputs are set to 50 Ω. The waveform shapes look reasonable and the CM noise is about 38mVpp on average.

In this second screen capture, the only difference is that OUT0B’s input has been set to 1 MΩ. Now both waveform shapes are larger and distorted.  Further, the CM noise has increased to about 344 mVpp on average.  This is almost an order of magnitude increase in CM noise.

Note that in these experiments, the time domain measurements are much more striking than the frequency domain measurements.  The phase noise differences might even have been glossed over in automated testing.  A good argument for a lab bench to have both types of instrumentation! 

Root Cause

Why is terminating only half of the output clock having such an impact? We don’t need to know all the details of the buffer’s design but a simplified model will provide some insight. Consider the figure below.

Components in the left hand side box are internal to the IC and illustrate a simplified model of a CML or Current Mode Logic driver that can be made compatible with several swing formats.  The AC-coupling caps are usually on the EVB and the load resistor R shown here is typically 50 Ω as for test equipment. Transmission lines are not illustrated but PCB traces and coaxial cable can all be assumed to be nominal 50 Ω.  (The AC coupled load terminations can also be regarded as 100 Ω differential across CLKP and CLKN where the center-tap CM voltage is GND.)

Some notable features include the following:

1. Current source Ibias sinks continuously.  To first order, current is switched through one of the input NMOS transistors when turned fully on depending on the input signals.
2. The internal termination resistors Rint are normally ~ R or perhaps 2*R to save current.
3. Common mode voltage Vcm is sensed at the center-point of 2 resistors Rcm. The value of these resistors is usually >> R, for example on the order of kΩ.
4. An op amp drives the Bias network so that the sensed Vcm is equal to Vref.
5. Each output voltage swing is based on Vsupply minus the voltage drop swing across Rint as the current changes.

The driver is symmetric and designed for specific DC biasing over expected terminated operation. DC-coupled loads would need to have a common voltage exactly equal to Vcm in order to not impact the intended bias.  This is why we need to AC-couple to instrument loads.

However, even if we are AC-coupled, if we don’t have symmetric loads, then the driver will be imbalanced and the result is that the output common mode voltage Vcm will be modulated which can impact biasing and operation.  In this particular case the CM feedback circuit is clearly unable to keep up. The performance of the measured terminated half-circuit is degraded by the operation of the unterminated half-circuit.  

Crosstalk

Half-terminated differential outputs can even impact neighboring output driver performance in subtle ways. In this experiment, we continue to work with an Si5345 EVB as before.  The phase noise plot below is for OUT0 set to nominal 161.1328125 MHz as before with OUT0B terminated.  Adjacent channel OUT1/OUT1B is set to nominal 2 times that or 322.265625 MHz. Both polarities are properly terminated. The 12 kHz to 20 MHz phase jitter measured 94.32 fs averaged over 5 sweeps. Spurs are depicted in dBc so we can see the details.

The next phase noise plot is for OUT0 again, under previous conditions, except this time neighboring output OUT1B is unterminated. There is not a significant increase in phase jitter. However, we have clearly introduced 2 new spurs above the powerline frequencies region as annotated below.

These were identified in the instrument spur list as 140.374 kHz at -104.874 dBc and 4.90 MHz at -108.235 dBc. There is no obvious mathematical relationship yet this is a consistent result for this board and configuration. For wireless applications interested in the reason for every spur we can at least attribute these to the adjacent channel’s improper termination.

Termination Options

There are a number of termination options for our evaluation boards, and similar application boards, depending on what’s available at your bench.  These include:

1. Use a differential limiting amplifier or balun to convert a differential clock in to a single-ended clock.
2. Connect each polarity in to a 50 Ω instrument input.
3. Terminate each unmeasured polarity using an SMA 50 RF load termination.

If one is attempting to make careful measurements on a 12 output evaluation board that could call for 24 – 1 or 23 SMA terminations. That’s a fair number. So what to do?

One approach is to just make sure that the nearest channel output clocks to the measured clock are terminated. That cuts the quantity down quite a lot. The other is to use RF pads or attenuators as described in the next section.

Attenuators as Lab Expedient Terminations

In our lab we have many multi-channel clock EVBs which can consume a large quantity of terminations during testing. If a lot of us are working in the lab simultaneously, we can’t always terminate every clock exactly the way we would like.  So another approach is to use a high value RF pad or attenuator as a lab expedient termination.

Commercially available attenuators are PI attenuators made up of a 3-resistor network. That is, the resistor network resembles the Greek letter "pi".  The first resistor R1 is shunted to GND, followed by R2 in series, followed by another R1 shunted to GND.

Using an online calculator such as at https://www.microwaves101.com/calculators/858-attenuator-calculator we can calculate the R1 and R2 values and the resulting effective Rload assuming no connection past the attenuator. The table below lists the effective load using 6 dB, 10 dB, and 20 dB terminations.

You can see that for increasing attenuator values the effective impedance looking in to the attenuator alone increases.  By 20 dB attenuation it’s an almost perfect termination. This can be very handy at times.  The results using this technique are indistinguishable from purpose-built terminations.

Conclusion

I hope you have enjoyed this Timing 101 article. I’ve given you some insight as to why it’s a best practice to terminate even unmeasured differential outputs.  And provided a tip for using an attenuator as a lab expedient termination if necessary.

As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 101 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,

Kevin

Hello,

It is possible to write to the output driver control registers to dynamically control the cross point.

However, this operation is asynchronous and may result in either widening of a pulse or a runt pulse at the point of switching.

Let me know if you have any other questions.

Best Regards,

Jui

Hello,

It is possible to write to the output driver control registers to dynamically control the cross point.

However, this operation is asynchronous and may result in either widening of a pulse or a runt pulse at the point of switching.

Let me know if you have any other questions.

Best Regards,

Jui