Introduction

In the previous Timing 201 article, Timing 201 #7: The Case of the Dueling PLLs – Part 1, I referred to a Silicon Labs white paper that describes Silicon Labs’ DSPLL nested dual-loop architecture as used in the Si538x wireless jitter attenuators. I first discussed the general motivation for a dual-loop PLL and compared the cascaded (series) dual-loop PLL versus the nested dual-loop PLL architectures.

The practical advantages of the nested dual-loop approach in this example were to reduce the number of tuned oscillators from 2 to 1 and to eliminate the need for a sensitive external voltage control line. The tradeoff for a nested feedback control loop is that the inner loop must be faster than the outer loop. If the loop speeds (or bandwidths) are comparable, then the loops will contend or “duel” with each other.

In this Part 2 follow-up post, I will discuss in more detail how to calculate the phase noise of both these dual-loop PLL approaches.

Some Simplifying Assumptions

To emphasize the basic ideas without getting bogged down in too much detail, I will make the following simplifying assumptions:

1. Jitter generation, i.e., intrinsic PLL noise, is negligible. I only care about how the PLLs filter their respective phase noise sources, and how they contribute to the output clock phase noise.
2. Phase noise scaling is not needed. Assume that the phase noise data I use is taken at the same carrier frequency for both PLLs. For example, it’s as if you had a 54 MHz XO or VCXO, and the input and output clock frequencies were all 54 MHz, and the VCO phase noise had been scaled down to 54 MHz. (Otherwise you would need to scale the phase noise data.)
3. Identical phase noise sources will be used to compare the two topologies. In particular, the XO and VCXO phase noise will be assumed to be identical. This is generally not the case as VCXOs are usually noisier than XOs for the same nominal frequency. Why this assumption is being taken will be made clear later in this article.
4. The PLL acts as a low pass filter (LPF) or high pass filter (HPF) to the input and VCO phase noise respectively. The filter is modeled with the corner frequency at the bandwidth (BW) frequency. The filter skirt slope or steepness magnitude is 20 dB/dec x the PLL order. So, a 2nd order PLL will be modeled with 40 dB/dec filter slopes.    

Series Dual-Loop Phase Noise Calculations

The figure below is from the cited white paper and previous post. The two PLLs are in series with each other.  

You will recall that the first PLL, PLL1, is narrowband (NB) and the second PLL, PLL2, is wideband. To calculate the phase noise, we will go left to right through the following steps.

1. Low pass filter the input clock phase noise based on PLL1’s bandwidth (BW).
2. High pass filter the VCXO phase noise based on PLL1’s BW.
3. Add their contributions together in a power sense to yield the total PLL1 phase noise input to PLL2.
4. Low pass filter the input to PLL2 based on PLL2’s BW.
5. High pass filter the VCO phase noise based on PLL2’s BW.
6. Finally, add these last two contributions together in a power sense to yield the total output phase noise

These calculations have been done in the attached spreadsheet Timing_201_7_The_Case_of_the_Dueling_PLLs - Part 2.xlsx. See the “Series Dual-Loop” worksheet. The PLLs are assumed to be 2nd order with the NB PLL BW = 100 Hz and the WB PLL BW = 1 MHz. These parameters can be changed in the spreadsheet, but practically speaking, NB PLLs will be on the order of mHz to kHz. WB PLLs are typically 500 kHz to 2 MHz. 

The resulting plot is as follows.

Nested Dual-Loop Phase Noise Calculations

The figure below is also repeated from the cited white paper and previous post. In this case, the two PLLs are nested with respect to each other. 

Now the inner loop (IL) PLL is WB and the outer loop (OL) PLL is NB. To calculate the phase noise, we will proceed from the “inside out” through the following steps.

1. Low pass filter the XO phase noise based on the IL PLL’s BW.
2. High pass filter the VCO phase noise based on the IL PLL’s BW.
3. Add their contributions together in a power sense to yield the total IL phase noise. Recall that the IL PLL acts as the “VCO” of the OL PLL.
4. Low pass filter the input phase noise based on the OL PLL’s BW.
5. High pass filter the total IL phase noise based on the OL PLL’s BW.
6. Add these last two contributions together in a power sense to yield the total output phase noise. 

These calculations have also been done in the attached spreadsheet Timing_201_7_The_Case_of_the_Dueling_PLLs - Part 2.xlsx. As before, to keep things “apples to apples”, the PLLs are assumed to be 2nd order with the NB PLL BW = 100 Hz and the WB PLL BW = 1 MHz.  See the “Nested Dual-Loop” worksheet. The resulting plot is as follows.

You will note how similar these plots are to each other. Let’s overlay the output phase noise plots together for comparison.
 

Series versus Nested Dual-Loop Phase Noise Plots

The output phase noise plots are overlaid on top of each other for direct comparison. As shown, they look identical. Further, if you experiment with the bandwidths of each PLL, for each topology, the best output phase noise is generally obtained by making PLL1 (or OL PLL) and PLL2 (or IL PLL) narrowband and wideband respectively. Even apart from stability considerations, both topologies benefit from wide separation between the bandwidths.  

Why the Topological Equivalence?

This result is not necessarily to be expected so let’s walk through the steps again and compare the approaches.

1. The total series dual-loop phase noise can be written out as:

LPF_WB (LPF_NB (Input) + HPF_NB (VCXO)) + HPF_WB (VCO)
LPF_WB * LPF_NB (Input) + LPF_WB * HPF_NB (VCXO) + HPF_WB (VCO)

The use of WB and NB notation versus PLL1, PLL2, IL PLL, and OL PLL is to help us make direct comparison between the two sets of calculations. LPF_WB means apply a wideband low pass filter to the phase noise in parenthesis. Two filter terms multiplied indicates applying both filters. 

2. Similarly, the total nested dual-loop phase noise can be written out as:

LPF_NB (Input) + HPF_NB (LPF_WB (XO) + HPF_WB (VCO))
LPF_NB (Input) + HPF_NB * LPF_WB (XO) + HPF_NB * HPF_WB (VCO)

3. If the bandwidths involved are the same, and the VCXO phase noise equals the XO phase noise, then the center terms above are equivalent. These can be thought of as the “bandpass” terms.
    
4. Further, assuming sufficient separation between bandwidths, we can make the following approximations:

LPF_WB * LPF_NB (Input) ≈ LPF_NB (Input)
HPF_NB * HPF_WB (VCO) ≈ HPF_WB (VCO)

In other words, the NB LPF and the WB HPF dominate the calculations for these LPF and HPF terms. This is why these topologies produce equivalent total phase noise when all else is equal.
 

Conclusion

I hope you have enjoyed this Timing 201 article. In this Part 2 follow-up post, I have discussed in more detail how to calculate the phase noise of both the series and nested dual-loop approaches. Finally, by using a simplified example with widely separated bandwidths, we can see that the approaches are essentially equivalent. There are particular advantages to the nested dual-loop approach which arise from an alternate practical implementation that yields phase noise equivalent to the series dual-loop approach.  

As always, if you have topic suggestions or questions appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,
Kevin

Introduction

In the previous Timing 201 article, Timing 201 #7: The Case of the Dueling PLLs – Part 1, I referred to a Silicon Labs white paper that describes Silicon Labs’ DSPLL nested dual-loop architecture as used in the Si538x wireless jitter attenuators. I first discussed the general motivation for a dual-loop PLL and compared the cascaded (series) dual-loop PLL versus the nested dual-loop PLL architectures.

The practical advantages of the nested dual-loop approach in this example were to reduce the number of tuned oscillators from 2 to 1 and to eliminate the need for a sensitive external voltage control line. The tradeoff for a nested feedback control loop is that the inner loop must be faster than the outer loop. If the loop speeds (or bandwidths) are comparable, then the loops will contend or “duel” with each other.

In this Part 2 follow-up post, I will discuss in more detail how to calculate the phase noise of both these dual-loop PLL approaches.

Some Simplifying Assumptions

To emphasize the basic ideas without getting bogged down in too much detail, I will make the following simplifying assumptions:

1. Jitter generation, i.e., intrinsic PLL noise, is negligible. I only care about how the PLLs filter their respective phase noise sources, and how they contribute to the output clock phase noise.
2. Phase noise scaling is not needed. Assume that the phase noise data I use is taken at the same carrier frequency for both PLLs. For example, it’s as if you had a 54 MHz XO or VCXO, and the input and output clock frequencies were all 54 MHz, and the VCO phase noise had been scaled down to 54 MHz. (Otherwise you would need to scale the phase noise data.)
3. Identical phase noise sources will be used to compare the two topologies. In particular, the XO and VCXO phase noise will be assumed to be identical. This is generally not the case as VCXOs are usually noisier than XOs for the same nominal frequency. Why this assumption is being taken will be made clear later in this article.
4. The PLL acts as a low pass filter (LPF) or high pass filter (HPF) to the input and VCO phase noise respectively. The filter is modeled with the corner frequency at the bandwidth (BW) frequency. The filter skirt slope or steepness magnitude is 20 dB/dec x the PLL order. So, a 2nd order PLL will be modeled with 40 dB/dec filter slopes.    

Series Dual-Loop Phase Noise Calculations

The figure below is from the cited white paper and previous post. The two PLLs are in series with each other.  

You will recall that the first PLL, PLL1, is narrowband (NB) and the second PLL, PLL2, is wideband. To calculate the phase noise, we will go left to right through the following steps.

1. Low pass filter the input clock phase noise based on PLL1’s bandwidth (BW).
2. High pass filter the VCXO phase noise based on PLL1’s BW.
3. Add their contributions together in a power sense to yield the total PLL1 phase noise input to PLL2.
4. Low pass filter the input to PLL2 based on PLL2’s BW.
5. High pass filter the VCO phase noise based on PLL2’s BW.
6. Finally, add these last two contributions together in a power sense to yield the total output phase noise

These calculations have been done in the attached spreadsheet Timing_201_7_The_Case_of_the_Dueling_PLLs - Part 2.xlsx. See the “Series Dual-Loop” worksheet. The PLLs are assumed to be 2nd order with the NB PLL BW = 100 Hz and the WB PLL BW = 1 MHz. These parameters can be changed in the spreadsheet, but practically speaking, NB PLLs will be on the order of mHz to kHz. WB PLLs are typically 500 kHz to 2 MHz. 

The resulting plot is as follows.

Nested Dual-Loop Phase Noise Calculations

The figure below is also repeated from the cited white paper and previous post. In this case, the two PLLs are nested with respect to each other. 

Now the inner loop (IL) PLL is WB and the outer loop (OL) PLL is NB. To calculate the phase noise, we will proceed from the “inside out” through the following steps.

1. Low pass filter the XO phase noise based on the IL PLL’s BW.
2. High pass filter the VCO phase noise based on the IL PLL’s BW.
3. Add their contributions together in a power sense to yield the total IL phase noise. Recall that the IL PLL acts as the “VCO” of the OL PLL.
4. Low pass filter the input phase noise based on the OL PLL’s BW.
5. High pass filter the total IL phase noise based on the OL PLL’s BW.
6. Add these last two contributions together in a power sense to yield the total output phase noise. 

These calculations have also been done in the attached spreadsheet Timing_201_7_The_Case_of_the_Dueling_PLLs - Part 2.xlsx. As before, to keep things “apples to apples”, the PLLs are assumed to be 2nd order with the NB PLL BW = 100 Hz and the WB PLL BW = 1 MHz.  See the “Nested Dual-Loop” worksheet. The resulting plot is as follows.

You will note how similar these plots are to each other. Let’s overlay the output phase noise plots together for comparison.

Series versus Nested Dual-Loop Phase Noise Plots

The output phase noise plots are overlaid on top of each other for direct comparison. As shown, they look identical. Further, if you experiment with the bandwidths of each PLL, for each topology, the best output phase noise is generally obtained by making PLL1 (or OL PLL) and PLL2 (or IL PLL) narrowband and wideband respectively. Even apart from stability considerations, both topologies benefit from wide separation between the bandwidths.  

Why the Topological Equivalence?

This result is not necessarily to be expected so let’s walk through the steps again and compare the approaches.

1. The total series dual-loop phase noise can be written out as:

LPF_WB (LPF_NB (Input) + HPF_NB (VCXO)) + HPF_WB (VCO)
LPF_WB * LPF_NB (Input) + LPF_WB * HPF_NB (VCXO) + HPF_WB (VCO)

The use of WB and NB notation versus PLL1, PLL2, IL PLL, and OL PLL is to help us make direct comparison between the two sets of calculations. LPF_WB means apply a wideband low pass filter to the phase noise in parenthesis. Two filter terms multiplied indicates applying both filters. 

2. Similarly, the total nested dual-loop phase noise can be written out as:

LPF_NB (Input) + HPF_NB (LPF_WB (XO) + HPF_WB (VCO))
LPF_NB (Input) + HPF_NB * LPF_WB (XO) + HPF_NB * HPF_WB (VCO)

3. If the bandwidths involved are the same, and the VCXO phase noise equals the XO phase noise, then the center terms above are equivalent. These can be thought of as the “bandpass” terms.
    
4. Further, assuming sufficient separation between bandwidths, we can make the following approximations:

LPF_WB * LPF_NB (Input) ≈ LPF_NB (Input)
HPF_NB * HPF_WB (VCO) ≈ HPF_WB (VCO)

In other words, the NB LPF and the WB HPF dominate the calculations for these LPF and HPF terms. This is why these topologies produce equivalent total phase noise when all else is equal.

Conclusion

I hope you have enjoyed this Timing 201 article. In this Part 2 follow-up post, I have discussed in more detail how to calculate the phase noise of both the series and nested dual-loop approaches. Finally, by using a simplified example with widely separated bandwidths, we can see that the approaches are essentially equivalent. There are particular advantages to the nested dual-loop approach which arise from an alternate practical implementation that yields phase noise equivalent to the series dual-loop approach.  

As always, if you have topic suggestions or questions appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,
Kevin

Introduction

In the previous Timing 201 article, Timing 201 #7: The Case of the Dueling PLLs – Part 1, I referred to a Silicon Labs white paper that describes Silicon Labs’ DSPLL nested dual-loop architecture as used in the Si538x wireless jitter attenuators. I first discussed the general motivation for a dual-loop PLL and compared the cascaded (series) dual-loop PLL versus the nested dual-loop PLL architectures.

The practical advantages of the nested dual-loop approach in this example were to reduce the number of tuned oscillators from 2 to 1 and to eliminate the need for a sensitive external voltage control line. The tradeoff for a nested feedback control loop is that the inner loop must be faster than the outer loop. If the loop speeds (or bandwidths) are comparable, then the loops will contend or “duel” with each other.

In this Part 2 follow-up post, I will discuss in more detail how to calculate the phase noise of both these dual-loop PLL approaches.

Some Simplifying Assumptions

To emphasize the basic ideas without getting bogged down in too much detail, I will make the following simplifying assumptions:

1. Jitter generation, i.e., intrinsic PLL noise, is negligible. I only care about how the PLLs filter their respective phase noise sources, and how they contribute to the output clock phase noise.
2. Phase noise scaling is not needed. Assume that the phase noise data I use is taken at the same carrier frequency for both PLLs. For example, it’s as if you had a 54 MHz XO or VCXO, and the input and output clock frequencies were all 54 MHz, and the VCO phase noise had been scaled down to 54 MHz. (Otherwise you would need to scale the phase noise data.)
3. Identical phase noise sources will be used to compare the two topologies. In particular, the XO and VCXO phase noise will be assumed to be identical. This is generally not the case as VCXOs are usually noisier than XOs for the same nominal frequency. Why this assumption is being taken will be made clear later in this article.
4. The PLL acts as a low pass filter (LPF) or high pass filter (HPF) to the input and VCO phase noise respectively. The filter is modeled with the corner frequency at the bandwidth (BW) frequency. The filter skirt slope or steepness magnitude is 20 dB/dec x the PLL order. So, a 2nd order PLL will be modeled with 40 dB/dec filter slopes.    

Series Dual-Loop Phase Noise Calculations

The figure below is from the cited white paper and previous post. The two PLLs are in series with each other.  

You will recall that the first PLL, PLL1, is narrowband (NB) and the second PLL, PLL2, is wideband. To calculate the phase noise, we will go left to right through the following steps.

1. Low pass filter the input clock phase noise based on PLL1’s bandwidth (BW).
2. High pass filter the VCXO phase noise based on PLL1’s BW.
3. Add their contributions together in a power sense to yield the total PLL1 phase noise input to PLL2.
4. Low pass filter the input to PLL2 based on PLL2’s BW.
5. High pass filter the VCO phase noise based on PLL2’s BW.
6. Finally, add these last two contributions together in a power sense to yield the total output phase noise

These calculations have been done in the attached spreadsheet Timing_201_7_The_Case_of_the_Dueling_PLLs - Part 2.xlsx. See the “Series Dual-Loop” worksheet. The PLLs are assumed to be 2nd order with the NB PLL BW = 100 Hz and the WB PLL BW = 1 MHz. These parameters can be changed in the spreadsheet, but practically speaking, NB PLLs will be on the order of mHz to kHz. WB PLLs are typically 500 kHz to 2 MHz. 

The resulting plot is as follows.

Nested Dual-Loop Phase Noise Calculations

The figure below is also repeated from the cited white paper and previous post. In this case, the two PLLs are nested with respect to each other. 

Now the inner loop (IL) PLL is WB and the outer loop (OL) PLL is NB. To calculate the phase noise, we will proceed from the “inside out” through the following steps.

1. Low pass filter the XO phase noise based on the IL PLL’s BW.
2. High pass filter the VCO phase noise based on the IL PLL’s BW.
3. Add their contributions together in a power sense to yield the total IL phase noise. Recall that the IL PLL acts as the “VCO” of the OL PLL.
4. Low pass filter the input phase noise based on the OL PLL’s BW.
5. High pass filter the total IL phase noise based on the OL PLL’s BW.
6. Add these last two contributions together in a power sense to yield the total output phase noise. 

These calculations have also been done in the attached spreadsheet Timing_201_7_The_Case_of_the_Dueling_PLLs - Part 2.xlsx. As before, to keep things “apples to apples”, the PLLs are assumed to be 2nd order with the NB PLL BW = 100 Hz and the WB PLL BW = 1 MHz.  See the “Nested Dual-Loop” worksheet. The resulting plot is as follows.

You will note how similar these plots are to each other. Let’s overlay the output phase noise plots together for comparison.

Series versus Nested Dual-Loop Phase Noise Plots

The output phase noise plots are overlaid on top of each other for direct comparison. As shown, they look identical. Further, if you experiment with the bandwidths of each PLL, for each topology, the best output phase noise is generally obtained by making PLL1 (or OL PLL) and PLL2 (or IL PLL) narrowband and wideband respectively. Even apart from stability considerations, both topologies benefit from wide separation between the bandwidths.  

Why the Topological Equivalence?

This result is not necessarily to be expected so let’s walk through the steps again and compare the approaches.

1. The total series dual-loop phase noise can be written out as:

LPF_WB (LPF_NB (Input) + HPF_NB (VCXO)) + HPF_WB (VCO)
LPF_WB * LPF_NB (Input) + LPF_WB * HPF_NB (VCXO) + HPF_WB (VCO)

The use of WB and NB notation versus PLL1, PLL2, IL PLL, and OL PLL is to help us make direct comparison between the two sets of calculations. LPF_WB means apply a wideband low pass filter to the phase noise in parenthesis. Two filter terms multiplied indicates applying both filters. 

2. Similarly, the total nested dual-loop phase noise can be written out as:

LPF_NB (Input) + HPF_NB (LPF_WB (XO) + HPF_WB (VCO))
LPF_NB (Input) + HPF_NB * LPF_WB (XO) + HPF_NB * HPF_WB (VCO)

3. If the bandwidths involved are the same, and the VCXO phase noise equals the XO phase noise, then the center terms above are equivalent. These can be thought of as the “bandpass” terms.
    
4. Further, assuming sufficient separation between bandwidths, we can make the following approximations:

LPF_WB * LPF_NB (Input) ≈ LPF_NB (Input)
HPF_NB * HPF_WB (VCO) ≈ HPF_WB (VCO)

In other words, the NB LPF and the WB HPF dominate the calculations for these LPF and HPF terms. This is why these topologies produce equivalent total phase noise when all else is equal.

Conclusion

I hope you have enjoyed this Timing 201 article. In this Part 2 follow-up post, I have discussed in more detail how to calculate the phase noise of both the series and nested dual-loop approaches. Finally, by using a simplified example with widely separated bandwidths, we can see that the approaches are essentially equivalent. There are particular advantages to the nested dual-loop approach which arise from an alternate practical implementation that yields phase noise equivalent to the series dual-loop approach.  

As always, if you have topic suggestions or questions appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,
Kevin

Introduction

RF and microwave frequency synthesizers often employ multiple connected PLLs. These architectures trade off complexity in favor of improved phase noise, smaller frequency step size, and faster switching [1]. In timing applications we may also employ multiple PLLs to combine timing functions and/or shape phase noise.   

For example, the white paper, “Optimizing Clock Synthesis in Small Cells and Heterogeneous Networks”, describes Silicon Labs’ DSPLL dual-loop architecture as used in the Si538x wireless jitter attenuators intended for small cell applications [2].  This particular approach is a nested dual-loop as opposed to a cascaded (concatenated) dual-loop. There are definite advantages to this implementation and some important considerations.

One consideration is the necessary bandwidth relationship between the inner and outer loops. This topic leads to the play on words in the main title of this blog post, The Case of the Dueling PLLs.  A second consideration is the difference in how one analyzes the phase noise for such an architecture, which arises from the fundamental difference between these two approaches as explained below. 

General Motivation for a Dual-Loop PLL Architecture

As you may recall from a previous blog post, there are two basic PLL clock applications [3]:

• Clock Generator (aka clock multiplier, frequency multiplier, etc.)
• Jitter Attenuator (aka jitter cleaner)

Low noise references are input to clock generators, which are usually wide bandwidth (e.g., 100s kHz to MHz). By contrast, jittery clocks are input to jitter attenuators, which are usually narrow bandwidth on the order of kHz or less.

But what if your clock application requires both functions? The most straightforward approach is to cascade the two PLLs in series as discussed in the next section. 

Cascaded Dual-Loop PLL Architecture

The figure below, taken from the cited white paper, illustrates a single-chip, cascaded dual-loop architecture. (Note that this sense of the term cascade is different from classic control system terminology. Here we mean two PLLs concatenated or in series.)

In this case, the left hand PLL1 with an analog Voltage Controlled Xtal Oscillator (VCXO) is used as a narrow band jitter attenuator stage.  The jitter attenuated clock signal is then input to the right hand PLL2, which is used as a wide band clock generator stage. The VCXO need not be very high in frequency but should have good close-in phase noise. This generally means a high Q crystal, which is why this component is typically external to the IC. This necessitates an external control voltage signal to the VCXO.

The on-chip VCO needs to be high enough in frequency so that the divided down clock can yield the necessary output clock frequencies. It also should have low phase noise at high offset frequencies.

This particular example is depicted as all analog with several external filter components and sensitive traces. However, there is no intrinsic reason why a cascaded dual-loop architecture could not be implemented more digitally and with filtering on-chip.

Because the PLLs in the example above are in-series and independent, the total output phase noise can be calculated as a cascade of phase noise processing elements as described in [3].  

Nested Dual-Loop PLL Architecture

The figure below, also from the cited white paper, illustrates a nested dual-loop architecture. In classic control system terminology, this would actually be considered a variation of a cascade control system. For clarity, I will use the term nested here. Think of it as the PLL equivalent of nested Matryoshka dolls.

In this case, the inner loop (IL) PLL is being used as the “VCO” or rather the Digitally Controlled Oscillator (DCO) of the outer loop (OL) PLL. This is the fundamental difference between these two approaches, which will determine how one calculates the total phase noise.

How does this work?

1. The output of the OL digital loop filter modulates the return path of the IL.
2. The output of the IL VCO is in fact the fOUT in the diagram. In practice, this output frequency is divided further to yield the necessary output clocks.

What are the advantages to this approach?

In this particular pair of examples, we reduce the number of tuned oscillators from two (VCXO and VCO) down to one (XO and VCO). This eliminates the need for one of the loop filters (be it internal or external) and a sensitive voltage control line, which must otherwise be routed externally. This decrease in components makes for a more compact solution which reduces the overall PCB footprint.

Could you implement a nested dual-loop with a VCXO?

Yes, in principle. There is no intrinsic reason why you couldn’t implement a nested dual-loop architecture that also uses an external VCXO.  Such an approach might even make sense if a particular VCXO has better phase noise performance, perhaps at a higher frequency (update rate). However, you would lose the specific advantages discussed previously. This is why the Si538x wireless jitter attenuators do not support an external VCXO.

What exactly is the Duel?

In these types of nested feedback control loops, the inner loop must be faster than the outer loop. If the loop speeds are comparable, then the loops will contend or “duel” with each other.

In PLL terms the inner loop must have a wider bandwidth than the outer loop.  This should make intuitive sense if you consider the relative difference in impact of inserting a really slow “DCO” into an otherwise fast PLL versus inserting a really fast “DCO” into an otherwise slow PLL. The former case significantly impacts the PLL and may even have stability or locking issues due to inserted additional delay. By contrast, the latter case is not impacted significantly. This tells us that the inner loop must be the faster (wider bandwidth) clock multiplier and the outer loop must be the slower (narrow bandwidth) jitter attenuator. Further, it tells us that at start-up and during the lock process, we want the inner loop PLL to stabilize and lock before the outer loop.

Another way of thinking about this is to recall that PLLs function as a low pass filter for phase noise arising from any source in the loop, except when they function as a high pass filter to VCO phase noise. For the OL PLL to modulate the IL’s return path without attenuation, the signal must be well within the IL BW.  

Incidentally, if you want to estimate one quantity from another, such as frequency step rise time from PLL bandwidth, you may use this relationship:

Tr [10%-90%] * BW [3dB] ≈ 0.35

See for example, Howard Johnson’s discussion in the article, PLL Response Time [5].  Per his article, the time bandwidth product varies from 0.35 to 0.38, depending on whether the PLL behaves closer to a single-pole or double-pole response.

How much faster or wider bandwidth must the inner loop be?  In mechanical engineering and process control systems, the differences in nested loop speeds can be relatively small.  A mechanical IL may be 5x to 10x faster than a mechanical OL. See for example Danielle Collins’ servo loop article in [6].  However, in timing applications, the difference in bandwidths is typically much greater. Nested dual-loop IL BWs are typically on the order of MHz, whereas OL BWs can be on the order of 10 Hz to 1 kHz, so the ratio is closer to the IL being 1000x to 100,000x faster than the OL. 

Note that for Si538x devices, the IL BW is wide (~ 1 MHz), fixed, and optimized.  Because it is so wide, there is no jitter attenuation at the device’s XO inputs, i.e., the XA/XB pins. Therefore, we should be careful that noise and interference does not couple into the device via the XO circuit at these pins. This is why we recommend low phase noise XOs to be placed as close as possible to the device so as to minimize PCB trace lengths.

Can this idea be extended?

Yes, in principle. The servo control loop article cited earlier discusses a servo motor control with three nested loops, inside to outside as follows: current feedback, velocity feedback, and position feedback. Similarly, you can “triple nest loop” clock PLLs to shape the phase noise to track select input clocks with different phase noise characteristics over different frequency offsets. However, this particular approach is not utilized by the Si538x devices.  

Conclusion

I hope you have enjoyed this Timing 201 article. In the Part 2 follow-up post, I will discuss in more detail how to calculate the phase noise of the nested dual-loop approach using a simplified example.

As always, if you have topic suggestions or questions appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,
Kevin

References

[1] W. F. Egan, Advanced Frequency Synthesis by Phase Lock. Wiley, 2011. See for example section 7.1 regarding the Two-Loop Synthesizer where two loops interact via a mixer.

[2] Optimizing Clock Synthesis in Small Cells and Heterogeneous Networks
https://www.silabs.com/documents/public/white-papers/Silicon-Labs-Next-Generation-DSPLL-Technology-White-Paper---June-2015.pdf

[3] Timing 101 #11: The Case of the Noisy Source Clock Tree Part 1
https://www.silabs.com/community/blog.entry.html/2018/10/30/timing_101_11_the-2uqO

[4] Timing 101 #12: The Case of the Noisy Source Clock Tree Part 2
https://www.silabs.com/community/blog.entry.html/2018/12/21/timing_101_12_the-ikzY

[5] H. Johnson, PLL Response Time, High-Speed Digital Design Online Newsletter: Vol. 15 Issue 04,
http://www.sigcon.com/Pubs/news/15_04.htm

[6] D. Collins, Why is the bandwidth of a servo control loop important?, April 20, 2017, https://www.motioncontroltips.com/why-is-the-bandwidth-of-a-servo-control-loop-important/

Introduction

RF and microwave frequency synthesizers often employ multiple connected PLLs. These architectures trade off complexity in favor of improved phase noise, smaller frequency step size, and faster switching [1]. In timing applications we may also employ multiple PLLs to combine timing functions and/or shape phase noise.   

For example, the white paper, “Optimizing Clock Synthesis in Small Cells and Heterogeneous Networks”, describes Silicon Labs’ DSPLL dual-loop architecture as used in the Si538x wireless jitter attenuators intended for small cell applications [2].  This particular approach is a nested dual-loop as opposed to a cascaded (concatenated) dual-loop. There are definite advantages to this implementation and some important considerations.

One consideration is the necessary bandwidth relationship between the inner and outer loops. This topic leads to the play on words in the main title of this blog post, The Case of the Dueling PLLs.  A second consideration is the difference in how one analyzes the phase noise for such an architecture, which arises from the fundamental difference between these two approaches as explained below. 

General Motivation for a Dual-Loop PLL Architecture

As you may recall from a previous blog post, there are two basic PLL clock applications [3]:

• Clock Generator (aka clock multiplier, frequency multiplier, etc.)
• Jitter Attenuator (aka jitter cleaner)

Low noise references are input to clock generators, which are usually wide bandwidth (e.g., 100s kHz to MHz). By contrast, jittery clocks are input to jitter attenuators, which are usually narrow bandwidth on the order of kHz or less.

But what if your clock application requires both functions? The most straightforward approach is to cascade the two PLLs in series as discussed in the next section. 

Cascaded Dual-Loop PLL Architecture

The figure below, taken from the cited white paper, illustrates a single-chip, cascaded dual-loop architecture. (Note that this sense of the term cascade is different from classic control system terminology. Here we mean two PLLs concatenated or in series.)

In this case, the left hand PLL1 with an analog Voltage Controlled Xtal Oscillator (VCXO) is used as a narrow band jitter attenuator stage.  The jitter attenuated clock signal is then input to the right hand PLL2, which is used as a wide band clock generator stage. The VCXO need not be very high in frequency but should have good close-in phase noise. This generally means a high Q crystal, which is why this component is typically external to the IC. This necessitates an external control voltage signal to the VCXO.

The on-chip VCO needs to be high enough in frequency so that the divided down clock can yield the necessary output clock frequencies. It also should have low phase noise at high offset frequencies.

This particular example is depicted as all analog with several external filter components and sensitive traces. However, there is no intrinsic reason why a cascaded dual-loop architecture could not be implemented more digitally and with filtering on-chip.

Because the PLLs in the example above are in-series and independent, the total output phase noise can be calculated as a cascade of phase noise processing elements as described in [3].  

Nested Dual-Loop PLL Architecture

The figure below, also from the cited white paper, illustrates a nested dual-loop architecture. In classic control system terminology, this would actually be considered a variation of a cascade control system. For clarity, I will use the term nested here. Think of it as the PLL equivalent of nested Matryoshka dolls.

In this case, the inner loop (IL) PLL is being used as the “VCO” or rather the Digitally Controlled Oscillator (DCO) of the outer loop (OL) PLL. This is the fundamental difference between these two approaches, which will determine how one calculates the total phase noise.

How does this work?

1. The output of the OL digital loop filter modulates the return path of the IL.
2. The output of the IL VCO is in fact the fOUT in the diagram. In practice, this output frequency is divided further to yield the necessary output clocks.

What are the advantages to this approach?

In this particular pair of examples, we reduce the number of tuned oscillators from two (VCXO and VCO) down to one (XO and VCO). This eliminates the need for one of the loop filters (be it internal or external) and a sensitive voltage control line, which must otherwise be routed externally. This decrease in components makes for a more compact solution which reduces the overall PCB footprint.

Could you implement a nested dual-loop with a VCXO?

Yes, in principle. There is no intrinsic reason why you couldn’t implement a nested dual-loop architecture that also uses an external VCXO.  Such an approach might even make sense if a particular VCXO has better phase noise performance, perhaps at a higher frequency (update rate). However, you would lose the specific advantages discussed previously. This is why the Si538x wireless jitter attenuators do not support an external VCXO.

What exactly is the Duel?

In these types of nested feedback control loops, the inner loop must be faster than the outer loop. If the loop speeds are comparable, then the loops will contend or “duel” with each other.

In PLL terms the inner loop must have a wider bandwidth than the outer loop.  This should make intuitive sense if you consider the relative difference in impact of inserting a really slow “DCO” into an otherwise fast PLL versus inserting a really fast “DCO” into an otherwise slow PLL. The former case significantly impacts the PLL and may even have stability or locking issues due to inserted additional delay. By contrast, the latter case is not impacted significantly. This tells us that the inner loop must be the faster (wider bandwidth) clock multiplier and the outer loop must be the slower (narrow bandwidth) jitter attenuator. Further, it tells us that at start-up and during the lock process, we want the inner loop PLL to stabilize and lock before the outer loop.

Another way of thinking about this is to recall that PLLs function as a low pass filter for phase noise arising from any source in the loop, except when they function as a high pass filter to VCO phase noise. For the OL PLL to modulate the IL’s return path without attenuation, the signal must be well within the IL BW.  

Incidentally, if you want to estimate one quantity from another, such as frequency step rise time from PLL bandwidth, you may use this relationship:

Tr [10%-90%] * BW [3dB] ≈ 0.35

See for example, Howard Johnson’s discussion in the article, PLL Response Time [5].  Per his article, the time bandwidth product varies from 0.35 to 0.38, depending on whether the PLL behaves closer to a single-pole or double-pole response.

How much faster or wider bandwidth must the inner loop be?  In mechanical engineering and process control systems, the differences in nested loop speeds can be relatively small.  A mechanical IL may be 5x to 10x faster than a mechanical OL. See for example Danielle Collins’ servo loop article in [6].  However, in timing applications, the difference in bandwidths is typically much greater. Nested dual-loop IL BWs are typically on the order of MHz, whereas OL BWs can be on the order of 10 Hz to 1 kHz, so the ratio is closer to the IL being 1000x to 100,000x faster than the OL. 

Note that for Si538x devices, the IL BW is wide (~ 1 MHz), fixed, and optimized.  Because it is so wide, there is no jitter attenuation at the device’s XO inputs, i.e., the XA/XB pins. Therefore, we should be careful that noise and interference does not couple into the device via the XO circuit at these pins. This is why we recommend low phase noise XOs to be placed as close as possible to the device so as to minimize PCB trace lengths.

Can this idea be extended?

Yes, in principle. The servo control loop article cited earlier discusses a servo motor control with three nested loops, inside to outside as follows: current feedback, velocity feedback, and position feedback. Similarly, you can “triple nest loop” clock PLLs to shape the phase noise to track select input clocks with different phase noise characteristics over different frequency offsets. However, this particular approach is not utilized by the Si538x devices.  

Conclusion

I hope you have enjoyed this Timing 201 article. In the Part 2 follow-up post, I will discuss in more detail how to calculate the phase noise of the nested dual-loop approach using a simplified example.

As always, if you have topic suggestions or questions appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,
Kevin

References

[1] W. F. Egan, Advanced Frequency Synthesis by Phase Lock. Wiley, 2011. See for example section 7.1 regarding the Two-Loop Synthesizer where two loops interact via a mixer.

[2] Optimizing Clock Synthesis in Small Cells and Heterogeneous Networks
https://www.silabs.com/documents/public/white-papers/Silicon-Labs-Next-Generation-DSPLL-Technology-White-Paper---June-2015.pdf

[3] Timing 101 #11: The Case of the Noisy Source Clock Tree Part 1
https://www.silabs.com/community/blog.entry.html/2018/10/30/timing_101_11_the-2uqO

[4] Timing 101 #12: The Case of the Noisy Source Clock Tree Part 2
https://www.silabs.com/community/blog.entry.html/2018/12/21/timing_101_12_the-ikzY

[5] H. Johnson, PLL Response Time, High-Speed Digital Design Online Newsletter: Vol. 15 Issue 04,
http://www.sigcon.com/Pubs/news/15_04.htm

[6] D. Collins, Why is the bandwidth of a servo control loop important?, April 20, 2017, https://www.motioncontroltips.com/why-is-the-bandwidth-of-a-servo-control-loop-important/

Introduction

Some five years ago, a customer contacted us thinking they needed to return a clock generator device that would often go into a continuously resetting state after power-up.  We had never heard of such unusual behavior and wondered if there was anything wrong with this particular unit’s POR (Power On Reset) circuit. 

Fortunately, the customer had a small PC board that frequently exhibited the behavior, and which they could ship to us for troubleshooting in our lab.  This enabled us to more quickly determine the root cause and verify the solution.

It turned out that an overlooked spec for a passive component located elsewhere on the board was causing large consequences for the customer’s application. The lessons learned are generally applicable and the subject of this blog article, The Case of the Autonomously Resetting Clock Generator.

BLUF (Bottom Line Up Front)

The clock generator’s POR circuit was not at fault. In fact, it was behaving exactly as it should. Rather, an external 3.3 V regulator circuit was marginally stable. Oscillations on the 3.3 V rail could be sufficiently large to trigger autonomous resets.    

Browsing the Power Supply Voltages

The customer board took in +12 V and regulated this down to the +3.3 V and +1.8 V rails required by the Si5341 clock generator.  I used a lab power supply with pushbutton Output On/Off to provide the necessary +12 V input. This allowed me to manually and conveniently power cycle many times in order to observe and contrast a passing versus failing (continuously resetting) power-up event. The series of oscilloscope screen captures below display the 3.3 V (orange trace) at the top and the 1.8 V (blue trace) at the bottom.

The figure below shows the nominally settled behavior of the 3.3 V and 1.8 V after a failed power-up.  The 1.8 V supply is completely accurate. However, the 3.3 V supply is clearly oscillating and even periodically dropping down to about 2.4 V, far below the POR trip threshold. 

What about those occasions where the part successfully powers up? Per the figure below, both the 3.3 V and 1.8 V rails are at their nominal targets but the 3.3 V supply appears much noisier. This is another clue that the 3.3 V regulator circuit may be marginally stable.

I then looked at the start-up behavior. When the device fails, the 3.3 V supply starts oscillating straight away.

Even when the unit successfully powers up, as depicted below, the 3.3 V supply exhibits overshoot before settling down to a noisy nominal voltage.

An Informative Vendor Data Sheet

The customer was using a 500 mA LDO (Low Drop Out) regulator in a SOT-23-5 package. Reading the vendor’s data sheet, I noticed that the typical application drawing showed the output capacitor as a 2.2 uF tantalum.  Further, the data sheet explicitly stated that the output capacitor needed an ESR of about 1 Ω and that ultra-low ESR caps could cause oscillation.

Inspecting the output cap on the customer’s board revealed that it was a ceramic capacitor. These can have an ESR with an order of magnitude less than an electrolytic capacitor. So that suggested the next experiment to try.

Demonstrating the Fix

We hacked in a 1 Ω resistor in series with the ceramic capacitor in order to emulate the approximate ESR of a tantalum capacitor. A close-up photo of the hack is shown below. The brown component in the upper part of the “elbow” is the existing capacitor. The component marked “01Y” is the 1 Ω resistor.  

The hack was ugly but effective:

As the resulting screen cap shows above, the 3.3 V supply is much less noisy and the start-up transient is very small and quickly damped out. After many attempts, no autonomous resets were observed, current draw was as expected, and the device always yielded output clocks.  This outcome was good enough for the customer to take over and do additional verification testing for their particular application.

Some Lessons Learned

This Timing 201 case exemplifies several lessons learned. These are listed below, going from the general to the specific.

1. If you have a significantly puzzling problem, and can ship us a failing PC board, that can greatly speed up the overall debug process. I realize that may not always be possible due to availability, expense, intellectual property, or power/control issues. Reducing a failing board down to the lowest populated version may help mitigate some of these concerns.
2. When troubleshooting any functional device issue, it’s always worth double-checking the supply voltages. Regulator instabilities, more subtle than this case, may even show up as increased output clock phase noise or spurs.
3. Be aware that relatively older LDO regulators may have been designed for and require higher ESR caps than relatively newer LDO regulators.  The particular vendor used by this customer sells LDO regulators of both varieties, i.e. those that require 1 Ω ESR output stability caps and those that do not.
4. Finally, it’s a good idea to make sure that schematics and BOMs call out exactly what LDO output capacitor is needed so that no one accidentally orders and installs the wrong type.

Conclusion

I hope you have enjoyed this Timing 201 article.  

As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,
Kevin

Introduction

Some five years ago, a customer contacted us thinking they needed to return a clock generator device that would often go into a continuously resetting state after power-up.  We had never heard of such unusual behavior and wondered if there was anything wrong with this particular unit’s POR (Power On Reset) circuit. 

Fortunately, the customer had a small PC board that frequently exhibited the behavior, and which they could ship to us for troubleshooting in our lab.  This enabled us to more quickly determine the root cause and verify the solution.

It turned out that an overlooked spec for a passive component located elsewhere on the board was causing large consequences for the customer’s application. The lessons learned are generally applicable and the subject of this blog article, The Case of the Autonomously Resetting Clock Generator.

BLUF (Bottom Line Up Front)

The clock generator’s POR circuit was not at fault. In fact, it was behaving exactly as it should. Rather, an external 3.3 V regulator circuit was marginally stable. Oscillations on the 3.3 V rail could be sufficiently large to trigger autonomous resets.    

Browsing the Power Supply Voltages

The customer board took in +12 V and regulated this down to the +3.3 V and +1.8 V rails required by the Si5341 clock generator.  I used a lab power supply with pushbutton Output On/Off to provide the necessary +12 V input. This allowed me to manually and conveniently power cycle many times in order to observe and contrast a passing versus failing (continuously resetting) power-up event. The series of oscilloscope screen captures below display the 3.3 V (orange trace) at the top and the 1.8 V (blue trace) at the bottom.

The figure below shows the nominally settled behavior of the 3.3 V and 1.8 V after a failed power-up.  The 1.8 V supply is completely accurate. However, the 3.3 V supply is clearly oscillating and even periodically dropping down to about 2.4 V, far below the POR trip threshold. 

What about those occasions where the part successfully powers up? Per the figure below, both the 3.3 V and 1.8 V rails are at their nominal targets but the 3.3 V supply appears much noisier. This is another clue that the 3.3 V regulator circuit may be marginally stable.

I then looked at the start-up behavior. When the device fails, the 3.3 V supply starts oscillating straight away.

Even when the unit successfully powers up, as depicted below, the 3.3 V supply exhibits overshoot before settling down to a noisy nominal voltage.

An Informative Vendor Data Sheet

The customer was using a 500 mA LDO (Low Drop Out) regulator in a SOT-23-5 package. Reading the vendor’s data sheet, I noticed that the typical application drawing showed the output capacitor as a 2.2 uF tantalum.  Further, the data sheet explicitly stated that the output capacitor needed an ESR of about 1 Ω and that ultra-low ESR caps could cause oscillation.

Inspecting the output cap on the customer’s board revealed that it was a ceramic capacitor. These can have an ESR with an order of magnitude less than an electrolytic capacitor. So that suggested the next experiment to try.

Demonstrating the Fix

We hacked in a 1 Ω resistor in series with the ceramic capacitor in order to emulate the approximate ESR of a tantalum capacitor. A close-up photo of the hack is shown below. The brown component in the upper part of the “elbow” is the existing capacitor. The component marked “01Y” is the 1 Ω resistor.  

The hack was ugly but effective:

As the resulting screen cap shows above, the 3.3 V supply is much less noisy and the start-up transient is very small and quickly damped out. After many attempts, no autonomous resets were observed, current draw was as expected, and the device always yielded output clocks.  This outcome was good enough for the customer to take over and do additional verification testing for their particular application.

Some Lessons Learned

This Timing 201 case exemplifies several lessons learned. These are listed below, going from the general to the specific.

1. If you have a significantly puzzling problem, and can ship us a failing PC board, that can greatly speed up the overall debug process. I realize that may not always be possible due to availability, expense, intellectual property, or power/control issues. Reducing a failing board down to the lowest populated version may help mitigate some of these concerns.
2. When troubleshooting any functional device issue, it’s always worth double-checking the supply voltages. Regulator instabilities, more subtle than this case, may even show up as increased output clock phase noise or spurs.
3. Be aware that relatively older LDO regulators may have been designed for and require higher ESR caps than relatively newer LDO regulators.  The particular vendor used by this customer sells LDO regulators of both varieties, i.e. those that require 1 Ω ESR output stability caps and those that do not.
4. Finally, it’s a good idea to make sure that schematics and BOMs call out exactly what LDO output capacitor is needed so that no one accidentally orders and installs the wrong type.

Conclusion

I hope you have enjoyed this Timing 201 article.  

As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,
Kevin

Introduction

Some five years ago, a customer contacted us thinking they needed to return a clock generator device that would often go into a continuously resetting state after power-up.  We had never heard of such unusual behavior and wondered if there was anything wrong with this particular unit’s POR (Power On Reset) circuit. 

Fortunately, the customer had a small PC board that frequently exhibited the behavior, and which they could ship to us for troubleshooting in our lab.  This enabled us to more quickly determine the root cause and verify the solution.

It turned out that an overlooked spec for a passive component located elsewhere on the board was causing large consequences for the customer’s application. The lessons learned are generally applicable and the subject of this blog article, The Case of the Autonomously Resetting Clock Generator.

BLUF (Bottom Line Up Front)

The clock generator’s POR circuit was not at fault. In fact, it was behaving exactly as it should. Rather, an external 3.3 V regulator circuit was marginally stable. Oscillations on the 3.3 V rail could be sufficiently large to trigger autonomous resets.    

Browsing the Power Supply Voltages

The customer board took in +12 V and regulated this down to the +3.3 V and +1.8 V rails required by the Si5341 clock generator.  I used a lab power supply with pushbutton Output On/Off to provide the necessary +12 V input. This allowed me to manually and conveniently power cycle many times in order to observe and contrast a passing versus failing (continuously resetting) power-up event. The series of oscilloscope screen captures below display the 3.3 V (orange trace) at the top and the 1.8 V (blue trace) at the bottom.

The figure below shows the nominally settled behavior of the 3.3 V and 1.8 V after a failed power-up.  The 1.8 V supply is completely accurate. However, the 3.3 V supply is clearly oscillating and even periodically dropping down to about 2.4 V, far below the POR trip threshold. 

What about those occasions where the part successfully powers up? Per the figure below, both the 3.3 V and 1.8 V rails are at their nominal targets but the 3.3 V supply appears much noisier. This is another clue that the 3.3 V regulator circuit may be marginally stable.

I then looked at the start-up behavior. When the device fails, the 3.3 V supply starts oscillating straight away.

Even when the unit successfully powers up, as depicted below, the 3.3 V supply exhibits overshoot before settling down to a noisy nominal voltage.

An Informative Vendor Data Sheet

The customer was using a 500 mA LDO (Low Drop Out) regulator in a SOT-23-5 package. Reading the vendor’s data sheet, I noticed that the typical application drawing showed the output capacitor as a 2.2 uF tantalum.  Further, the data sheet explicitly stated that the output capacitor needed an ESR of about 1 Ω and that ultra-low ESR caps could cause oscillation.

Inspecting the output cap on the customer’s board revealed that it was a ceramic capacitor. These can have an ESR with an order of magnitude less than an electrolytic capacitor. So that suggested the next experiment to try.

Demonstrating the Fix

We hacked in a 1 Ω resistor in series with the ceramic capacitor in order to emulate the approximate ESR of a tantalum capacitor. A close-up photo of the hack is shown below. The brown component in the upper part of the “elbow” is the existing capacitor. The component marked “01Y” is the 1 Ω resistor.  

The hack was ugly but effective:

As the resulting screen cap shows above, the 3.3 V supply is much less noisy and the start-up transient is very small and quickly damped out. After many attempts, no autonomous resets were observed, current draw was as expected, and the device always yielded output clocks.  This outcome was good enough for the customer to take over and do additional verification testing for their particular application.

Some Lessons Learned

This Timing 201 case exemplifies several lessons learned. These are listed below, going from the general to the specific.

1. If you have a significantly puzzling problem, and can ship us a failing PC board, that can greatly speed up the overall debug process. I realize that may not always be possible due to availability, expense, intellectual property, or power/control issues. Reducing a failing board down to the lowest populated version may help mitigate some of these concerns.
2. When troubleshooting any functional device issue, it’s always worth double-checking the supply voltages. Regulator instabilities, more subtle than this case, may even show up as increased output clock phase noise or spurs.
3. Be aware that relatively older LDO regulators may have been designed for and require higher ESR caps than relatively newer LDO regulators.  The particular vendor used by this customer sells LDO regulators of both varieties, i.e. those that require 1 Ω ESR output stability caps and those that do not.
4. Finally, it’s a good idea to make sure that schematics and BOMs call out exactly what LDO output capacitor is needed so that no one accidentally orders and installs the wrong type.

Conclusion

I hope you have enjoyed this Timing 201 article.  

As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,
Kevin

Introduction

As I write this, many of us around the world are working under COVID-19 quarantine conditions. So before diving in, I want to wish all of you and yours the very best of health. Please take care of yourselves out there!   

Now to recap so far:
In Part 1 of this series, I discussed the parasitic PLL in which an independent oscillator can couple energy into a Phase-Locked Loop’s (PLL’s) VCO which can impact the PLL’s output frequency and phase. I then reviewed some basic injection theory including the concept of injection lock range. In Part 2, I discussed how to minimize injection sensitivity. In this last and final Part 3, I will discuss the topic of measuring injection sensitivity, and what one can do with that information.

ILBW (Injection Lock Bandwidth)

The figure below was presented in Part 1 and follows Wolaver’s development culminating in this equation with the important takeaways noted.

Wolaver treated the injection constant or gain KINJ as the injection lock range. It is useful to think of this lock range as the Injection Lock Bandwidth or ILBW to contrast it with the PLL’s loop bandwidth BW. In order to minimize the risk of injection locking we want

ILBW < BW

In fact, we would prefer for ILBW << BW. A practical empirical rule of thumb we have applied is the following

            ILBW <= 0.3 * BW

We will apply this rule of thumb in later example calculations.

ILBW Practical Issues

Let’s take another look at Wolaver’s equation for KINJ as the injection lock range aka the Injection Lock Bandwidth or ILBW. In the annotated figure below I call out some practical issues.

There are several difficulties that may arise when attempting to make direct calculations of this equation based on measurements of the individual factors:

• The quantities Q and the ratio PINJ/PT are not always well known.
• The frequency of the tank circuit fTANK is typically on the order of GHz to 10 GHz or more, which means we will need high frequency sources and probes.
   
• Probing directly at ICs may be difficult and/or require purpose-built test boards.

• HF scope probes may need calibrating to make measurements directly at fTANK.

Provided one can apply a calibrated high frequency interferer, it is often easier to measure the effective ILBW. The rest of this post will discuss a couple of ideas on how to do this.

ILBW Measurement Approaches

This post will discuss two different measurement approaches summarized in the table below. The first method applies an asynchronous aggressor source and uses the offset spur result measured on a spectrum analyzer to estimate the ILBW. The second method applies a synchronous aggressor source and measures the ILBW directly from a phase noise analyzer.

These methods will be demonstrated using older simpler architecture devices where injection may be conveniently observed. Modern clock devices are generally less susceptible to injection due to architecture, shielding, etc. The examples that follow will give an indication of what you might observe with classic narrow bandwidth single loop PLLs.

PLL Injection Sensitivity – Estimating ILBW via Asynchronous Injection

Using this first approach, we measure the spur that results on the output for a given asynchronous but near-synchronous injection applied to the device. The general idea is to configure the DUT as typical, using an input clock source that does not have significant harmonics at or near the PLL’s VCO frequency. Then apply an interferer or aggressor clock set near the VCO frequency to individual pins and determine the worst case.

The general test set-up used years ago for the Si53xx SONET devices was as follows:

1. Configure an Si53xx device for a nominal 622.08 MHz clock output resulting in the tank operating at 2.48832 GHz. 
2. Apply an input reference clock, e.g. 155.52 MHz, applied single-ended in to one of the CLKIN connectors.  A good sinusoidal source is used and then bandpass filtered in order to reject any additional harmonic components in the vicinity of the tank frequency. Thus the only significant interferer at the tank is the one purposely injected.
3. An interferer or aggressor clock set to 2.48834 GHz at -20 dBm drives a device pin through a an RF connector on a purpose-built PCB designed just for this test. On this board, device pins are AC coupled to RF connectors that are terminated in to 50 Ohms. 
4. Output clock measurement: The output clock and the resulting offset spur are measured using a spectrum analyzer. For the case where –20 dBm is applied directly as described, the offset spur will be in the –40 to –70 dBc or lower range depending on the device and the pin. Other than the supply pins having typical bypass capacitors, there were no I/O filtering or other injection lock mitigating features used on this test board.  

A general comment about probes: One can measure the voltage at device pins using a divide-by-10 high impedance differential probe, even if not specified to operate at the intended frequency, if carefully calibrated. Back when this data was collected the probes available had a 20 dB calibrated loss at 2.5 GHz.

So for a -20 dBm interferer we would expect a signal at the device pins as follows assuming no additional losses.

-20 dBm applied interferer
-20 dB due to divide-by-10 probe
-20 dB due to probe roll off at 2.5 GHz
----
-60 dBm measured at device pins

How can we use this technique to estimate the ILBW or Injection Lock Bandwidth? Here are the steps.

1. Apply an finj offset from ftank well outside the loop BW.
   In this example, the 20 kHz offset of the interferer is chosen for convenience to insure that the selection of loop BW is irrelevant.  Selecting the 800 Hz BW allows one to select an interferer with a lower offset frequency.
2. Measure the offset spur Pspur (dBc) versus the output clock.
3. Calculate Pspur_tank accounting for any output dividers.
4. Extrapolate ILBW for Pspur_tank = 0 dBc per the anticipated injection locking 20 dB/dec slope. (This is effectively calculating an intercept.)

PLL Injection Sensitivity – Example Estimated ILBW Calculations

The figure below shows the spectrum for an Si53xx SONET clock device configured for an output of 622.08 MHz together with the resulting injected spur. The DUT used a post VCO output divider N = 4 to yield output frequency f0 =  622.08 MHz. For this device, the DUT VCO frequency or ftank = 622.08 MHz x 4 = 2.48832 GHz.

Here are the example calculations in this instance:

1. We applied injection frequency finj = 2.48840 GHz or 80 kHz offset at -20 dBm.
2. The resulting output spur frequency fspur = 622.10 MHz or 20 kHz offset at -62.4 dBc.
3. Accounting for the N=4 output divider, Pspur_tank = -62.4 dBc + 20*log10(4) = -50.4 dBc.
4. Set P_spur_tank – 20*log10 (f_ILBW/f_offset) = 0 dBc and solve for f_ILBW

• -50.4 dBc – 20*log10 (f_ILBW/f_offset) = 0 dBc
• -20*log10 (f_ILBW/f_offset) = 50.4
• f_ILBW/20kHz = [10^(50.4/-20)]
• f_ILBW = [10^(50.4/-20)] * 20e3
• f_ILBW or simply ILBW = 60.4 Hz

The minimum operating BW for this part is 800 Hz. Applying the rule of thumb ILBW is much less than 0.3 * 800 Hz or 240 Hz. Therefore we do not expect injection lock to be an issue.

Another way of looking at the problem is to ask:  For a given loop BW selection how large a spur, referred to the tank frequency, am I allowed to have using the rule of thumb?

            Pspur_tank (max allowed)      = 20*log10(fILBW/foffset) dBc 
                                                            = 20*log10(0.3*fBW/foffset) dBc 

 Using the same example situation as before:

            Pspur_tank (max allowed)      = 20*log10(0.3*800/20000) dBc
                                                            = -38.4 dBc

Injection Lock Tolerance

We can apply the information described above, together with worst case pin data, to estimate how much interfering signal the device pins can tolerate before injection lock may cause jitter to be an issue.  The worst case data suggested that the interferer amplitude at a pin may be as low as –50 dBm and yield a spur as high as –44 dBc.

Using this worst case pin assumption, then the worst case spur at the tank would be:

            Pspur_tank_wc = -44 dBc + 20*log10(4) = -44 dBc + 12 dB = -32 dBc

Recall that the Pspur_tank (max allowed) for an 800 Hz BW is -38.4 dBc and so we must decrease the allowable interferer signal strength at the pins to –50 dBm – (38.4-32) = -56.4 dBm. As a practical matter, we should then decrease this by at least another 6 dB to add margin. This suggests the following criterion for the Si53xx clock chips:

The interferer strength at a device pin should not exceed –62 dBm.

This conservative criterion means that Si53xx clock devices should not injection lock unless an extraneous 2.5 GHz source can inject a signal > –62 dBm at an individual pin.

What if we had an especially noisy application where this limit was exceeded? If significant interfering energy is present, filtering, attenuation, and good layout can reduce the level of conducted interference on sensitive pins.

PLL Injection Sensitivity – Measuring ILBW via Synchronous Injection

In this second approach, we apply a synchronous interferer and observe the impact of injection lock directly on the phase noise plot. 

The figure below illustrates the basic idea.

• An injection locked oscillator’s phase noise is reduced from its free running state.
• The intersection of the phase noise plots is the single-sided ILBW.
• This method uses a low phase noise independent synchronous source to directly measure the ILBW for a specific amount of injection.

Engineers who are familiar with phase noise plots will recognize that the injection locked oscillator phase noise truly looks “locked” just as if it was in a designed PLL, and not in an incidental or parasitic counterpart.

Evaluation Board Experiments Setup

To demonstrate the phase noise analyzer approach, I used an RF Synthesizer evaluation board which has convenient VCO frequencies for my purposes. The figure below summarizes the test set-up.

In this case however, I did not want to use a purpose-built board or inject an interfering signal at all the pins. Instead, I decided to simply remove the bypass caps and inject the synchronous interferer directly in to the power supply. You can think of this as a high frequency extension to PSRR or Power Supply Rejection Ratio testing. In other words a sort of IPRR or Injection Pulling Rejection Ratio test. 

Here are the main points:

1. The Device Under Test (DUT) was the venerable Silicon Labs Si4133 which is a dual band RF Synthesizer with Type I PLLs, integrated VCOs, and which works with external inductors.
2. The board used was the Si4133M-EVB with power supply bypass capacitors removed.
3. The IPRR1MHz measured ≈ 22 dB down to < 0 dB going from f0 = 473 MHz to 1886 MHz.

Evaluation Board Experiments Phase Noise Plots

The phase noise plots below were based on data measured on an old Agilent (now Keysight) JS-500 rack system which is an E5500 superset. One of the features that’s nice about this older equipment is that the user has direct access to the measurement PLL’s loop BW. This allows one to measure very noisy and even open loop phase noise plots.

You can read the ILBW directly from the intersection of the locked phase noise plots versus the open loop phase noise plot. As suggested by the Wolaver equation, increasing the power of the injected signal results in a wider ILBW which would restrict the loop bandwidths at which the device would operate.

In these experiments, ILBW only approached 10 kHz even with a +10 dBm synchronous signal injected in to the power supply. Note that the Si4133 is not operated as a jitter attenuator but rather as a clock generator with a good quality TCXO as the reference source or input clock and a typical operating bandwidth ≈ 200 kHz.  

Estimated versus Measured ILBW

In the 2009 ACISC paper in the references, I compared both methods applied to the RF Synthesizer and obtained good agreement. See the figure below comparing ILBW as estimated based on 1 MHz offsets versus direct measurement.

Injection Lock Troubleshooting

Injection lock may be an issue if the device’s clock output jitter is out of spec, cannot be accounted for given the input clock’s phase noise, and the device’s Jitter Transfer Function, and exhibits an unexpected jitter distribution. A suspicious example of the latter would be a bimodal jitter distribution.   

A general troubleshooting procedure is listed below. Try each of these items in turn and check to see if the situation improves. 

1. Widen the selected loop BW. If the input clock has low phase noise and widening the BW improves the output clock jitter then injection lock may be present.
2. Assuming the input clock is not excessively noisy, check to make sure that it does not have significant amounts of energy at the tank frequency. If it does, substitute a low phase noise clock, filtered to eliminate components at the tank frequency.
3. If there is a follow up PLL with a narrower bandwidth than the DUT try changing the BW relationship either by widening the receiver PLL BW or narrowing the transmitter BW.
4. If injection lock is confirmed and items 2-3 have no effect then at this point it is a matter of identifying and turning off other potential aggressor clocks on the board, just as one would with any other EMI investigation.

In the particular case of Si53xx clock ICs, application note AN59 describes generally good layout and filtering practices.

Summary

In this and the previous related blog posts, I have reviewed injection pulling and lock, injection mitigation, and practical measurements. Here are the main points to sum up:

1. Two oscillators in close proximity tend to phase lock to each other. This can includes PLL VCOs.
2. Injection by independent clocks can impact PLL output phase noise and jitter. In this context, independent clocks can be near-synchronous asynchronous clocks or synchronous out-of-phase clocks.
3. Higher frequency and narrow bandwidth single-loop PLLs are more susceptible to injection lock.
4. Injection Lock Bandwidth or ILBW is a practical measure of injection sensitivity.
5. Reduce ILBW by minimizing the coupling of interferer clocks with a fundamental or harmonic at or very near the PLL’s VCO frequency.

References

The same references that applied to the previous posts apply here. They are repeated again below for convenience.

Some of the material covered here was presented at the Austin Conference on Integrated Systems and Circuits (ACISC) in 2009. If you are interested, you can email me to request a copy of the paper “Practical Issues Measuring and Minimizing Injection Pulling in Board-level Oscillator and PLL Applications” and accompanying slides.

As mentioned previously, the best practical overall book treatment I am familiar with is in Wolaver’s text:

• D.H. Wolaver, Phase-Locked Loop Circuit Design, 1991, Prentice-Hall, pp. 97-104. 

This is a slim volume for a PLL book but it punches well above its weight in terms of information.  

Here are several foundational papers worth reading on the topic of injection.

• R. Adler, “A Study of Locking Phenomena in Oscillators,” Proc. IRE and Waves and Electrons, vol. 34 (June 1946), pp. 351-357. 
• K. Kurokawa, "Injection Locking of Microwave Solid-State Oscillators," Proc, IEEE 61, 1386 (1973).
• B. Razavi, “A Study of Injection Pulling and Locking in Oscillators,” IEEE J. Solid-State Circuits, vol. 39, pp. 1415-1424, September 2004. 

If you have favorite references you would like to share, please pass them along to me.

Conclusion

I hope you have enjoyed this Timing 201 series on injection lock.  

As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,
Kevin

Introduction

In the last Timing 201 post, I discussed the parasitic Phase-Locked Loop (PLL) in which an independent oscillator can couple energy in to a PLL’s VCO so as to influence or even take over the PLL’s output frequency and phase. I then reviewed some basic injection theory, including the concept of injection lock range.

Given the amount of material I would like to cover, I am going to follow-up that post with two more articles.  This installment, Part 2, will discuss how to minimize injection sensitivity generally. Part 3, to come later, will cover the topic of measuring injection sensitivity.  

A Brief Review

Per the last article, injection pulling or locking refers to when one independent oscillator disturbs or locks the frequency and phase of another independent near-synchronous oscillator. We then reviewed injection theory after Wolaver (1991) culminating in this equation with the important take-aways noted.

ILBW (Injection Lock Bandwidth)

Wolaver treated the injection constant or gain KINJ as the injection lock range. It is useful to regard this lock range as the Injection Lock Bandwidth (ILBW) to contrast it with the PLL’s loop bandwidth (BW). From here on, I will use this nomenclature. The bottom line is that, in order to minimize the risk of injection locking, we want BW > ILBW.  Ideally, BW would be significantly greater than the PLL’s ILBW.

The factors in the formula suggest where we might run in to trouble. For example, LC tank oscillators, especially when integrated, have much lower Q compared to crystal oscillators. Further, the trend is for higher and higher frequency clocks. The resonant tank frequency itself is usually dictated by something on the order of 2 times the maximum 50% duty cycle output clock frequency we would like to support. So we should be on guard for this issue when considering narrow band (NB) and high frequency low-Q VCO tank circuit PLLs.

So why don’t we routinely run in to injection problems today? Well you still can, if you are rolling your own NB discrete synchronous PLLs and especially if you co-locate them. This article series is in part an attempt to warn you of some possible concerns.

Board and IC designers have learned over the years to adopt injection resistant practices and PLL topologies. First, let’s begin by considering some typical injection mechanisms. 

Injection Mechanisms

There are several common injection mechanisms in which aggressor oscillator noise may couple in to a tank oscillator circuit. The first two listed are suggested by the figure below:

1. Power supply noise transmitted through the PCB or IC substrate
2. EM fields directly coupled in to the tank circuit
3. Conducted noise via board traces and IC pins

We can mitigate, or reduce the impact, of injection by directly addressing these injection mechanisms and/or by using more injection resistant system-level approaches.

Injection Mitigation via Good EMC Design

Injection can be regarded as a special topic within the field of EMC (Electromagnetic Compatibility). We can minimize injection noise power applied at the tank for each of these mechanisms using good practices for designers cognizant of general Electromagnetic Interference (EMI) issues.

1. Power supply noise through PCB or IC substrate

• Power supply bypassing or filtering

2. EM fields directly coupling to the tank circuit

• Employing separation and shielding

3. Conducted noise via board traces and IC pins

• Applying signal filtering and good PCB layout: planes, short traces, etc.

All of the above methods attack the problem by reducing the strength of the aggressor noise PINJ.  However, in addition to these direct approaches, there are some other more systemic ways of minimizing injection problems.

Injection Mitigation via Thoughtful Frequency Planning

You may recall that I mentioned the general problem of injection pulling and locking arises when working with signals and oscillators that are synchronous or nearly so. What do I mean by nearly-synchronous? A SONET application board with lots of clock I/O all running at or near SONET frequencies within a few ppm of each other is a classic example.

One approach, if you have multiple PLLs or clock devices co-located on the same printed circuit board, is to configure them so that the VCO frequencies are asynchronous from each other. For example, consider an application where you have two adjacent Si570 I2C-Programmable XOs on a PCB. You can minimize the risk of injection crosstalk (XTALK) by configuring the devices so that their internal DCOs or Digitally Controlled Oscillators are well off frequency from each other.

Consider the Si570 Detailed Block Diagram below taken from this datasheet.  In the diagram, HS_DIV refers to the DCO High Speed Divider with possible values [4-7, 9, 11].  N1 is the CLKOUT Output Divider with allowed values [1] and [2, 4, 6, …, 27].  Finally, the datasheet constrains the DCO frequency to 4.850 GHz £ fosc £ 5.67 GHz. Given these constraints, there can often be multiple frequency plan solutions that output the same clock frequency.

For example, the DCOs can be made significantly asynchronous even when the output clocks are identical in frequency. Here are two valid Si570 configurations that both yield f1 = 155.52 MHz outputs.

• fosc1 = f1 x HS_DIV x N1 = 155.52 MHz x 4 x 8 = 4.976640 GHz.
• fosc2 = f1 x HS_DIV x N1 = 155.52 MHz x 9 x 4 = 5.598720 GHz.

In this instance, each DCO frequency is asynchronous, greatly minimizing the risk of injection XTALK.

Injection Mitigation via Beneficial Clock Architectures

One architectural approach is to simply minimize the number of PLLs, and therefore VCOs, with associated tank circuits, that might be susceptible to injection XTALK.

An example clock generator that minimizes the number of PLLs is the Si5338 I2C-Programmable Any-Frequency, Any-Output Quad Clock Generator. The functional block diagram below is taken from the Si5338 datasheet.

The Si5338 design consists primarily of a single wideband PLL with a bandwidth typically 1.6 MHz, followed by 4 “MultiSynth” dividers which can support four independent output clocks. The MultiSynth dividers are Silicon Labs’ proprietary low jitter fractional dividers that incorporate phase error correction. This whitepaper discusses this approach. Please note that there are other lower jitter clock generators employing similar architectures, with more clock I/O, such as the Si5332.

A second injection resistant architectural approach is to embed the potentially susceptible VCO tank circuit in a wideband PLL. (Recall that we want BW > ILBW.) An example jitter attenuator device that improves injection rejection in this way is the Si5380 which uses a nested dual loop architecture as shown in the diagram below. This illustration is taken from the “Optimizing Clock Synthesis in Small Cells and Heterogeneous Networks” whitepaper.

In this topology, the LC tank circuit VCO is integrated in a wideband (fast) inner loop which itself acts as the DCO for a narrowband (slow) outer loop. Please note that the Si5380 has been superseded by the more flexible, higher performance Si5386.

References

The same references that applied to the previous Timing 201 post apply here. They are listed below, for convenience.

Some material covered here was presented at the Austin Conference on Integrated Systems and Circuits (ACISC) in 2009. If you are interested, email me to request a copy of the paper “Practical Issues Measuring and Minimizing Injection Pulling in Board-level Oscillator and PLL Applications” and accompanying slides.

As mentioned previously, the best practical overall book treatment of injection lock that I am familiar with is in Wolaver’s text:

• D.H. Wolaver, Phase-Locked Loop Circuit Design, 1991, Prentice-Hall, pp. 97-104. 

This is a slim volume for a PLL book but it punches well above its weight in terms of information.  

Here are several foundational papers worth reading on the topic of injection.

• R. Adler, “A Study of Locking Phenomena in Oscillators,” Proc. IRE and Waves and Electrons, vol. 34 (June 1946), pp. 351-357. 
• K. Kurokawa, "Injection Locking of Microwave Solid-State Oscillators," Proc, IEEE 61, 1386 (1973).
• B. Razavi, “A Study of Injection Pulling and Locking in Oscillators,” IEEE J. Solid-State Circuits, vol. 39, pp. 1415-1424, September 2004. 

If you have favorite references you would like to share, please pass them along to me.

Conclusion

To recap, there are a number of ways that IC, board, and system designers can reduce the risk of injection pulling or injection lock.

1. Good EMC Design
2. Thoughtful Frequency Planning
3. Beneficial Clock Architectures
   • Minimize the number of PLLs and therefore VCOs
   • Embed susceptible VCOs in a wideband PLL

Looking ahead, it turns out it is often not practical to straightforwardly calculate the ratio of PINJ/PT and therefore KINJ or ILBW. Next time I will review how one may measure ILBW in the lab.

I hope you have enjoyed this Timing 201 article. As always, if you have topic suggestions, or there are questions appropriate for this blog you would like answered, please send them to kevin.smith@silabs.com with the words “Timing 201” in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,
Kevin