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kgsmith
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Timing 201 #4: The Case of the Parasitic PLL - Part 2 on Blog
Introduction In the last Timing 201 post, I discussed the parasitic Phase-Locked Loop (PLL) in which an independent oscillator can couple energy in to a PLL’s VCO so as to influence or even take over the PLL’s output frequency and phase. I then reviewed some basic injection theory, including the concept of injection lock range. Given the amount of material I would like to cover, I am going to follow-up that post with two more articles. This installment, Part 2, will discuss how to minimize injection sensitivity generally. Part 3, to come later, will cover the topic of measuring injection sensitivity. A Brief Review Per the last article, injection pulling or locking refers to when one independent oscillator disturbs or locks the frequency and phase of another independent near-synchronous oscillator. We then reviewed injection theory after Wolaver (1991) culminating in this equation with the important take-aways noted.
ILBW (Injection Lock Bandwidth) Wolaver treated the injection constant or gain KINJ as the injection lock range. It is useful to regard this lock range as the Injection Lock Bandwidth (ILBW) to contrast it with the PLL’s loop bandwidth (BW). From here on, I will use this nomenclature. The bottom line is that, in order to minimize the risk of injection locking, we want BW > ILBW. Ideally, BW would be significantly greater than the PLL’s ILBW. The factors in the formula suggest where we might run in to trouble. For example, LC tank oscillators, especially when integrated, have much lower Q compared to crystal oscillators. Further, the trend is for higher and higher frequency clocks. The resonant tank frequency itself is usually dictated by something on the order of 2 times the maximum 50% duty cycle output clock frequency we would like to support. So we should be on guard for this issue when considering narrow band (NB) and high frequency low-Q VCO tank circuit PLLs. So why don’t we routinely run in to injection problems today? Well you still can, if you are rolling your own NB discrete synchronous PLLs and especially if you co-locate them. This article series is in part an attempt to warn you of some possible concerns. Board and IC designers have learned over the years to adopt injection resistant practices and PLL topologies. First, let’s begin by considering some typical injection mechanisms. Injection Mechanisms There are several common injection mechanisms in which aggressor oscillator noise may couple in to a tank oscillator circuit. The first two listed are suggested by the figure below:
We can mitigate, or reduce the impact, of injection by directly addressing these injection mechanisms and/or by using more injection resistant system-level approaches. Injection Mitigation via Good EMC Design Injection can be regarded as a special topic within the field of EMC (Electromagnetic Compatibility). We can minimize injection noise power applied at the tank for each of these mechanisms using good practices for designers cognizant of general Electromagnetic Interference (EMI) issues.
All of the above methods attack the problem by reducing the strength of the aggressor noise PINJ. However, in addition to these direct approaches, there are some other more systemic ways of minimizing injection problems. Injection Mitigation via Thoughtful Frequency Planning You may recall that I mentioned the general problem of injection pulling and locking arises when working with signals and oscillators that are synchronous or nearly so. What do I mean by nearly-synchronous? A SONET application board with lots of clock I/O all running at or near SONET frequencies within a few ppm of each other is a classic example. One approach, if you have multiple PLLs or clock devices co-located on the same printed circuit board, is to configure them so that the VCO frequencies are asynchronous from each other. For example, consider an application where you have two adjacent Si570 I2C-Programmable XOs on a PCB. You can minimize the risk of injection crosstalk (XTALK) by configuring the devices so that their internal DCOs or Digitally Controlled Oscillators are well off frequency from each other. Consider the Si570 Detailed Block Diagram below taken from this datasheet. In the diagram, HS_DIV refers to the DCO High Speed Divider with possible values [4-7, 9, 11]. N1 is the CLKOUT Output Divider with allowed values [1] and [2, 4, 6, …, 27]. Finally, the datasheet constrains the DCO frequency to 4.850 GHz £ fosc £ 5.67 GHz. Given these constraints, there can often be multiple frequency plan solutions that output the same clock frequency.
For example, the DCOs can be made significantly asynchronous even when the output clocks are identical in frequency. Here are two valid Si570 configurations that both yield f1 = 155.52 MHz outputs.
In this instance, each DCO frequency is asynchronous, greatly minimizing the risk of injection XTALK. Injection Mitigation via Beneficial Clock Architectures One architectural approach is to simply minimize the number of PLLs, and therefore VCOs, with associated tank circuits, that might be susceptible to injection XTALK. An example clock generator that minimizes the number of PLLs is the Si5338 I2C-Programmable Any-Frequency, Any-Output Quad Clock Generator. The functional block diagram below is taken from the Si5338 datasheet.
The Si5338 design consists primarily of a single wideband PLL with a bandwidth typically 1.6 MHz, followed by 4 “MultiSynth” dividers which can support four independent output clocks. The MultiSynth dividers are Silicon Labs’ proprietary low jitter fractional dividers that incorporate phase error correction. This whitepaper discusses this approach. Please note that there are other lower jitter clock generators employing similar architectures, with more clock I/O, such as the Si5332. A second injection resistant architectural approach is to embed the potentially susceptible VCO tank circuit in a wideband PLL. (Recall that we want BW > ILBW.) An example jitter attenuator device that improves injection rejection in this way is the Si5380 which uses a nested dual loop architecture as shown in the diagram below. This illustration is taken from the “Optimizing Clock Synthesis in Small Cells and Heterogeneous Networks” whitepaper. In this topology, the LC tank circuit VCO is integrated in a wideband (fast) inner loop which itself acts as the DCO for a narrowband (slow) outer loop. Please note that the Si5380 has been superseded by the more flexible, higher performance Si5386.
References The same references that applied to the previous Timing 201 post apply here. They are listed below, for convenience. Some material covered here was presented at the Austin Conference on Integrated Systems and Circuits (ACISC) in 2009. If you are interested, email me to request a copy of the paper “Practical Issues Measuring and Minimizing Injection Pulling in Board-level Oscillator and PLL Applications” and accompanying slides. As mentioned previously, the best practical overall book treatment of injection lock that I am familiar with is in Wolaver’s text:
This is a slim volume for a PLL book but it punches well above its weight in terms of information. Here are several foundational papers worth reading on the topic of injection.
If you have favorite references you would like to share, please pass them along to me. Conclusion To recap, there are a number of ways that IC, board, and system designers can reduce the risk of injection pulling or injection lock.
Looking ahead, it turns out it is often not practical to straightforwardly calculate the ratio of PINJ/PT and therefore KINJ or ILBW. Next time I will review how one may measure ILBW in the lab. I hope you have enjoyed this Timing 201 article. As always, if you have topic suggestions, or there are questions appropriate for this blog you would like answered, please send them to kevin.smith@silabs.com with the words “Timing 201” in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on. Cheers,
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10 days ago |
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kgsmith
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Posted
Timing 201 #3: The Case of the Parasitic PLL - Part 1 on Blog
Introduction Anyone who has had training or experience in high frequency electronics is familiar with the concepts of parasitic capacitance and inductance. These are the unintended “hidden schematic” components that you get when assembling physically realizable circuits. Modeling these elements explicitly may be necessary depending on the application and desired accuracy. It turns out that an independent oscillator can couple energy in to a Phase-Locked Loop’s (PLL’s) VCO so as to influence or even take over the PLL’s output frequency and phase. This is the case of the parasitic PLL. It is a special case of injection as described below. In this post, I will review the basic theory and modeling for this phenomenon. My interest is not in walking through the derivations but rather noting the highlights of the results. This basic bench-level knowledge of injection is useful when designing or applying oscillators and PLLs. Cited references are listed at the end for further study. In the next post I will discuss how to measure injection sensitivity and provide for its mitigation. Motivation Injection locking can actually be useful in certain specific applications such as injection-locked frequency dividers. See Razavi (2004) for example. However, there are several reasons why unintentional injection in PLL frequency synthesis is undesirable:
Unless otherwise noted, this post assumes that the applications of interest involve PLLs which rely on LC resonant tank oscillators. Such circuits are in common use and subject to power supply coupling and external interference. Their Q or quality factor is high enough to yield reasonably good phase noise performance but low enough that injection can be an issue. The emphasis will be on a board level perspective though the same general principles may be applied at lower integration levels. Oscillator Injection Injection pulling or locking refers to when one independent oscillator disturbs or locks the frequency and phase of another independent near-synchronous oscillator. Using crosstalk terminology, the victim oscillator’s frequency is pulled by the aggressor or interferer’s frequency. In the extreme, one oscillator is pulled all the way to lock at another oscillator’s frequency. It is well known that oscillators in close proximity tend to lock to each other. The figure below gives the basic idea. Mechanical injection locking was first observed in pendulum clocks by Dutch scientist Christiaan Huygens in the 17th century. For a modern revisit of this work, see this online paper from Georgia Tech: http://schatzlab.gatech.edu/Library/Bennett2002.pdf.
This is commonly demonstrated in educational settings using metronomes on shared rolling or fixed platforms. See for example http://salt.uaa.alaska.edu/physics_public/metro.html. I have done this myself and it’s a neat demonstration. Analogous behavior can happen in electronics when working with tuned oscillator circuits. Two classic papers on this subject are Adler (1946) and Kurokawa (1973). Independent Oscillators In this context, the term independent oscillator can refer to either asynchronous clocks that are very close (or harmonically close) in frequency or to synchronous clocks that are out of phase. Further, the notion of independence can be extended to synchronous clocks with different phase noise characteristics. The most important example of the latter case is a PLL’s input and output clock domains. Consider a noisy input clock provided to a narrow bandwidth “clean-up” PLL that yields the same frequency output clock. The jitter attenuated output is synchronous to the input clock but independent from a phase noise point of view. Basic Injection Theory My favorite practical treatment on this topic is in Wolaver (1991) and I lean heavily on his work in what follows. Consider the following figures adapted from his book. I use “INJ” subscripts for injection quantities and “T” subscripts for tank quantities for clarity.
In these figures, the following terms apply:
For sustained oscillation the tank circuit must yield a compensating phase shift -Phi1 from VT to V’T and Phi1 = Phi2. The phase of the transfer function VT/ V’T is plotted in the bottom figure. The bottom line is that an injected voltage will result in a phase shift in the oscillator loop. Oscillator Injection Lock Range By assuming that VINJ << VT, Wolaver derived an injection constant or gain where injection acts like a 1st order PLL. Below is a version of Wolaver’s derivation for KINJ with one term re-cast as the square root of a power ratio.
In this figure, the following terms apply:
The derivation suggests several important take-aways, all called out in the figure.
The model below is adapted from Wolaver’s simplest small signal model for a PLL with injection. This version breaks out the injection constant contributions where the angle α represents the phase difference between the injected signal and the input signal.
There are two important features to note in this model.
This last item is most important. Wolaver suggests K > 4 * KINJ. All else being equal, relatively NB (narrow bandwidth) PLLs are more susceptible. Looking ahead to Part 2, the relationship between the nominal (uninjected) and injected PLL BWs will prove useful both in terms of troubleshooting and mitigation. You may recall a previous blog post Timing 101: The Case of the PLL’s VCO High Pass Transfer Function. It pointed out that a relatively wide bandwidth PLL can be used to attenuate VCO intrinsic phase noise. Likewise, a wide bandwidth PLL is also useful to suppress external influences on the VCO such as injection pulling or locking. References Some of the material covered here was presented at the Austin Conference on Integrated Systems and Circuits (ACISC) in 2009. If you are interested, you can email me to request a copy of the paper “Practical Issues Measuring and Minimizing Injection Pulling in Board-level Oscillator and PLL Applications” and accompanying slides. As mentioned previously, the best practical overall book treatment I am familiar with is in Wolaver’s text:
This is a slim volume for a PLL book but it punches well above its weight in terms of information. Here are several foundational papers worth reading on the topic of injection.
If you have favorite references you would like to share, please pass them along to me. Conclusion I hope you have enjoyed this Timing 201 article. Next time, I will follow-up on measuring and minimizing injection sensitivity. As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on. Cheers,
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10 days ago |
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kgsmith
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Posted
Timing 201 #4: The Case of the Parasitic PLL - Part 2 on Blog
Introduction In the last Timing 201 post, I discussed the parasitic Phase-Locked Loop (PLL) in which an independent oscillator can couple energy in to a PLL’s VCO so as to influence or even take over the PLL’s output frequency and phase. I then reviewed some basic injection theory, including the concept of injection lock range. Given the amount of material I would like to cover, I am going to follow-up that post with two more articles. This installment, Part 2, will discuss how to minimize injection sensitivity generally. Part 3, to come later, will cover the topic of measuring injection sensitivity. A Brief Review Per the last article, injection pulling or locking refers to when one independent oscillator disturbs or locks the frequency and phase of another independent near-synchronous oscillator. We then reviewed injection theory after Wolaver (1991) culminating in this equation with the important take-aways noted.
ILBW (Injection Lock Bandwidth) Wolaver treated the injection constant or gain KINJ as the injection lock range. It is useful to regard this lock range as the Injection Lock Bandwidth (ILBW) to contrast it with the PLL’s loop bandwidth (BW). From here on, I will use this nomenclature. The bottom line is that, in order to minimize the risk of injection locking, we want BW > ILBW. Ideally, BW would be significantly greater than the PLL’s ILBW. The factors in the formula suggest where we might run in to trouble. For example, LC tank oscillators, especially when integrated, have much lower Q compared to crystal oscillators. Further, the trend is for higher and higher frequency clocks. The resonant tank frequency itself is usually dictated by something on the order of 2 times the maximum 50% duty cycle output clock frequency we would like to support. So we should be on guard for this issue when considering narrow band (NB) and high frequency low-Q VCO tank circuit PLLs. So why don’t we routinely run in to injection problems today? Well you still can, if you are rolling your own NB discrete synchronous PLLs and especially if you co-locate them. This article series is in part an attempt to warn you of some possible concerns. Board and IC designers have learned over the years to adopt injection resistant practices and PLL topologies. First, let’s begin by considering some typical injection mechanisms. Injection Mechanisms There are several common injection mechanisms in which aggressor oscillator noise may couple in to a tank oscillator circuit. The first two listed are suggested by the figure below:
We can mitigate, or reduce the impact, of injection by directly addressing these injection mechanisms and/or by using more injection resistant system-level approaches. Injection Mitigation via Good EMC Design Injection can be regarded as a special topic within the field of EMC (Electromagnetic Compatibility). We can minimize injection noise power applied at the tank for each of these mechanisms using good practices for designers cognizant of general Electromagnetic Interference (EMI) issues.
All of the above methods attack the problem by reducing the strength of the aggressor noise PINJ. However, in addition to these direct approaches, there are some other more systemic ways of minimizing injection problems. Injection Mitigation via Thoughtful Frequency Planning You may recall that I mentioned the general problem of injection pulling and locking arises when working with signals and oscillators that are synchronous or nearly so. What do I mean by nearly-synchronous? A SONET application board with lots of clock I/O all running at or near SONET frequencies within a few ppm of each other is a classic example. One approach, if you have multiple PLLs or clock devices co-located on the same printed circuit board, is to configure them so that the VCO frequencies are asynchronous from each other. For example, consider an application where you have two adjacent Si570 I2C-Programmable XOs on a PCB. You can minimize the risk of injection crosstalk (XTALK) by configuring the devices so that their internal DCOs or Digitally Controlled Oscillators are well off frequency from each other. Consider the Si570 Detailed Block Diagram below taken from this datasheet. In the diagram, HS_DIV refers to the DCO High Speed Divider with possible values [4-7, 9, 11]. N1 is the CLKOUT Output Divider with allowed values [1] and [2, 4, 6, …, 27]. Finally, the datasheet constrains the DCO frequency to 4.850 GHz £ fosc £ 5.67 GHz. Given these constraints, there can often be multiple frequency plan solutions that output the same clock frequency.
For example, the DCOs can be made significantly asynchronous even when the output clocks are identical in frequency. Here are two valid Si570 configurations that both yield f1 = 155.52 MHz outputs.
In this instance, each DCO frequency is asynchronous, greatly minimizing the risk of injection XTALK. Injection Mitigation via Beneficial Clock Architectures One architectural approach is to simply minimize the number of PLLs, and therefore VCOs, with associated tank circuits, that might be susceptible to injection XTALK. An example clock generator that minimizes the number of PLLs is the Si5338 I2C-Programmable Any-Frequency, Any-Output Quad Clock Generator. The functional block diagram below is taken from the Si5338 datasheet.
The Si5338 design consists primarily of a single wideband PLL with a bandwidth typically 1.6 MHz, followed by 4 “MultiSynth” dividers which can support four independent output clocks. The MultiSynth dividers are Silicon Labs’ proprietary low jitter fractional dividers that incorporate phase error correction. This whitepaper discusses this approach. Please note that there are other lower jitter clock generators employing similar architectures, with more clock I/O, such as the Si5332. A second injection resistant architectural approach is to embed the potentially susceptible VCO tank circuit in a wideband PLL. (Recall that we want BW > ILBW.) An example jitter attenuator device that improves injection rejection in this way is the Si5380 which uses a nested dual loop architecture as shown in the diagram below. This illustration is taken from the “Optimizing Clock Synthesis in Small Cells and Heterogeneous Networks” whitepaper. In this topology, the LC tank circuit VCO is integrated in a wideband (fast) inner loop which itself acts as the DCO for a narrowband (slow) outer loop. Please note that the Si5380 has been superseded by the more flexible, higher performance Si5386.
References The same references that applied to the previous Timing 201 post apply here. They are listed below, for convenience. Some material covered here was presented at the Austin Conference on Integrated Systems and Circuits (ACISC) in 2009. If you are interested, email me to request a copy of the paper “Practical Issues Measuring and Minimizing Injection Pulling in Board-level Oscillator and PLL Applications” and accompanying slides. As mentioned previously, the best practical overall book treatment of injection lock that I am familiar with is in Wolaver’s text:
This is a slim volume for a PLL book but it punches well above its weight in terms of information. Here are several foundational papers worth reading on the topic of injection.
If you have favorite references you would like to share, please pass them along to me. Conclusion To recap, there are a number of ways that IC, board, and system designers can reduce the risk of injection pulling or injection lock.
Looking ahead, it turns out it is often not practical to straightforwardly calculate the ratio of PINJ/PT and therefore KINJ or ILBW. Next time I will review how one may measure ILBW in the lab. I hope you have enjoyed this Timing 201 article. As always, if you have topic suggestions, or there are questions appropriate for this blog you would like answered, please send them to kevin.smith@silabs.com with the words “Timing 201” in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on. Cheers,
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11 days ago |
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kgsmith
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Posted Can the Si4133 AUXOUT be treated as an SPI MISO line? on Knowledge Base Show more |
Oct 07 2019, 11:52 PM |
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kgsmith
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Posted Can a single-ended external reference clock be connected to an Si534x/7x/8x/9x device's XB pin? on Knowledge Base Show more |
Oct 07 2019, 11:30 PM |
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kgsmith
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Updated
Timing 201 #2: The Case of the Phase Noise That Wasn’t - Part 2 on Blog
Introduction Hello and welcome to the latest article for the blog series, Timing 201. This is a sequel to the article Timing 201 #1: The Case of the Phase Noise That Wasn’t – Part 1. In this post, I follow-up on Part 1 and suggest that both a limiting amplifier and balun are useful accessories to minimize AM and make good phase noise measurements. I include some example data and close with a few rules of thumb. A Quick Review from Part 1 You will recall the basic idea we last explored was that AM (Amplitude Modulation) noise can impact phase noise measurements. (AM noise is the apparent “phase noise that isn’t”.) A spectrum analyzer cannot distinguish between AM and PM (Phase Modulation) or phase noise. Purpose-built phase noise measurement instrumentation can suppress but not eliminate AM to PM conversion. The use of a limiting amplifier can further reduce the impact of AM noise on phase noise measurement. This can be a valuable troubleshooting tool when investigating system-level clock noise and spurs. Example Limiting Amplifier AM Rejection First, a few words about the particular limiting amplifier used for data collection in this article. The ideal limiting amplifier or LA would be high gain, low noise, wideband, and modestly priced. That combination is hard to find. The sample LA used here is the Hittite (now Analog Devices) HMC750 which has a 3 dB bandwidth of 11 GHz. An evaluation board is available from distributors though it’s relatively expensive. There are other LAs available from other vendors, and if you buy units in quantity and/or roll your own PCB, you can certainly lower your costs. Two suggestions if you do use the Hittite evaluation board:
As a reminder, the time domain operation of the LA is illustrated as follows. Below left is a scope capture for a 100 MHz single-ended sinusoidal clock. The AM depth was 5% and the scope is set to infinite persistence. Below right is the same single-ended clock through the example limiting amplifier.
While the time domain operation is suggestive, AM rejection is better measured in the frequency domain. In the following measurements, a Keysight E5052B was used both as the measurement instrument and as a stand-in clock receiver. I employed a Keysight 33600A Waveform Generator, operating single-endedly, to apply AM at several frequencies and measured both the AM and phase noise spur amplitude. The carrier was 100 MHz and the AM depth was set to 1%. Getting a consistent AM spur above the noise floor was what I was looking for.
I then inserted the cited LA and repeated the same measurements.
Note the new noise columns that had to be added. The LA effectively eliminated the AM spur completely, reducing it to the noise floor. There is still a corresponding phase noise spur, reduced also. (Subsequent testing indicated this was incidental phase modulation from the source.) Here is a sample plot for the 100 kHz case with no intervening limiting amplifier. The phase noise window is displayed at the top and the AM noise window is displayed at the bottom. Marker 1 in each window is set at 100 kHz.
And here is a corresponding sample plot for the 100 kHz case when using the limiting amplifier. As I mentioned previously, the AM spur is eliminated which I was looking for. The corresponding phase noise spur dropped another 12 dB. For some reason, at least for this sample, the AM noise floor above 10 kHz is not flat as would be ideal.
In general, we should use a limiting amplifier if AM noise or spurs are significant with respect to phase noise. In a measurement system that can measure both, we typically want AM noise or spurs to be at least 10 dB below phase noise or spurs at the same offset frequencies. (We weren’t quite getting that in the first table above.) Ideally, the same would be true for the clock receiver accounting for its AM rejection. For example, if both the input clock’s AM noise floor and phase noise floor were the same at a particular offset frequency, then we would want the clock receiver to reject or attenuate AM noise further by 10 dB. This performance is not always specified and may need to be measured. It is also often a function of the input clock slew rate or rise/fall time. Differential Signaling A limiting amplifier is useful for removing AM from both single-ended and differential clocks. However, differential clocks are themselves an important approach to combating AM noise. One of the most important reasons for differential signaling on balanced lines is common mode (CM) noise rejection. Since most AM noise on differential signals is CM (e.g. due to power supplies) then differential receivers will tend to reject AM. This can be illustrated pictorially in the figures below. First, consider amplitude noise impressed upon a single-ended clock.
Now, consider the same amplitude noise impressed upon a differential clock.
There are several aspects to the diagram worth noting:
All of these will help to prevent CM AM noise from impacting the measurement. Unfortunately, most spectrum and phase noise analysis instruments have single-ended inputs and don’t directly support differential measurements. If we replace the receiver in the diagram with an instrument, what is the best approach? A ready measurement would be to route one differential clock polarity, e.g. CLKP, to the instrument and terminate the unmeasured polarity output, e.g. CLKN, in to 50 Ω. Generally you will want to AC-couple these so as to present roughly the same impedance. The necessity for balanced termination is discussed in Timing 101 #10: The Case of the Half-terminated Differential Output Clock. This is a valid measurement but is overly conservative as it neglects the advantage that would actually be experienced in a differential clock system. What we need is a device that will convert the differential signal to a single-ended signal. Such a device is known as a balun (taken from balanced to unbalanced). This could be in the form of an amplifier (sometimes called an active balun) or more typically a passive component. As an example of the latter, a classic transformer balun or voltage balun has a center-tapped winding on one side for converting 100 Ω differential to single-ended 50 Ω. The example balun used in these tests is the Tektronix (formerly Picosecond Pulse Labs) PSPL5310R. This is a phase matched balun which can operate from 4 MHz to 6.5 GHz. Unfortunately, for some reason, these are no longer available from Tektronix. Other vendors which sell baluns include MACOM, Marki Microwave, and Mini-Circuits. (This is not meant to be an inclusive and exhaustive list. These are just companies I am familiar with.) Look for a balun wideband enough to pass the necessary waveform with sufficient risetime and with good phase and amplitude balance. The old PSPL balun had anywhere from ± 0.5 to ± 2 degrees differential phase balance and ± 0.1 to +0.3/0.2 dB differential amplitude balance depending on the frequency range. Example DUT with AM Noise I have selected for a practical example one of my favorite “desert island” parts, the venerable Si570 which is an older generation programmable oscillator. It was the first 5 mm x 7 mm I2C programmable oscillator that could cover 10 MHz to 1.4 GHz. Radio amateurs may recognize this device as used in some “Softrock” SDR (Software Defined Radio) applications. Not only can it support such a wide frequency range but it can also be ordered with “real” LVPECL drivers. By this I mean it can drive DC-coupled LVPECL loads defined as 50 Ω terminated in to VDD – 2V. (By contrast, clock devices typically provide LVPECL compatible modes where they can supply the right swing when AC-coupled.) There is some CM (Common Mode) AM noise using this mode. However, this is mitigated when used differentially as intended. Below we will tabulate several measurement scenarios with and without a balun and LA. The DUT is an evaluation board with P/N 570AAA000121DG installed operating AC-coupled. This is a differential programmable XO with a 100 MHz starting frequency, output format 3.3V LVPECL. Here are the phase jitter results for various configurations.
The biggest bang for the buck so to speak was using a balun. That got us to the 300fs range or less which is what we expect this device to yield. (The closest Si570 datasheet spec is 360 fs typical for Fout from 125 to 500 MHz.) Here are a few plots to go with this table. First, the single-ended configuration with the highest phase jitter, over 600 fs. Note the several spurs above 1 MHz in both the AM and phase noise measurement windows.
Next is the balun only configuration which eliminates some spurs and drops the phase jitter roughly in half, i.e. below 300 fs.
Finally, here is the phase noise plot combining the DUT driving the LA differentially which in turn drives the balun connected to the E5052B. This plot eliminates all the spurs above 1 MHz and still keeps the phase noise floor mostly below -150 dBc/Hz beyond this offset frequency.
Virtual Limiting Amplifier Ignoring spurs, it is possible in principle to estimate the DUT’s post-LA phase noise performance by mathematically applying a “virtual limiting amplifier”, if you know what the LA AM noise floor will be and what the AM to PM conversion is for your instrument. However, that is a topic for another time. In practice, as one peels the onion to achieve lower and lower phase noise measurements, spurs play an increasingly larger role. This can be problematic for estimation purposes since even if the location of spurs can be predicted, often their amplitudes cannot. A Few Rules of Thumb Based on this and the previous Timing 201 post, here are a few suggested rules of thumb when making phase noise measurements on sources that may have AM noise:
Having a good limiting amplifier and a good balun on your bench can help you make more accurate phase noise and jitter measurements, and help distinguish the type of noise contributors you are dealing with. If you are working with differential clocks, you really should use a balun even if AM noise is not that significant. Conclusion I hope you have enjoyed this Timing 201 article. If you have a favorite balun or limiting amplifier you would like to share with others, please let me know. As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words “Timing 201” in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on. Cheers, Kevin |
Sep 26 2019, 8:00 PM |
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kgsmith
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Posted
Timing 201 #2: The Case of the Phase Noise That Wasn’t - Part 2 on Blog
Introduction Hello and welcome to the latest article for the blog series, Timing 201. This is a sequel to the article Timing 201 #1: The Case of the Phase Noise That Wasn’t – Part 1. In this post, I follow-up on Part 1 and suggest that both a limiting amplifier and balun are useful accessories to minimize AM and make good phase noise measurements. I include some example data and close with a few rules of thumb. A Quick Review from Part 1 You will recall the basic idea we last explored was that AM (Amplitude Modulation) noise can impact phase noise measurements. (AM noise is the apparent “phase noise that isn’t”.) A spectrum analyzer cannot distinguish between AM and PM (Phase Modulation) or phase noise. Purpose-built phase noise measurement instrumentation can suppress but not eliminate AM to PM conversion. The use of a limiting amplifier can further reduce the impact of AM noise on phase noise measurement. This can be a valuable troubleshooting tool when investigating system-level clock noise and spurs. Example Limiting Amplifier AM Rejection First, a few words about the particular limiting amplifier used for data collection in this article. The ideal limiting amplifier or LA would be high gain, low noise, wideband, and modestly priced. That combination is hard to find. The sample LA used here is the Hittite (now Analog Devices) HMC750 which has a 3 dB bandwidth of 11 GHz. An evaluation board is available from distributors though it’s relatively expensive. There are other LAs available from other vendors, and if you buy units in quantity and/or roll your own PCB, you can certainly lower your costs. Two suggestions if you do use the Hittite evaluation board:
As a reminder, the time domain operation of the LA is illustrated as follows. Below left is a scope capture for a 100 MHz single-ended sinusoidal clock. The AM depth was 5% and the scope is set to infinite persistence. Below right is the same single-ended clock through the example limiting amplifier.
While the time domain operation is suggestive, AM rejection is better measured in the frequency domain. In the following measurements, a Keysight E5052B was used both as the measurement instrument and as a stand-in clock receiver. I employed a Keysight 33600A Waveform Generator, operating single-endedly, to apply AM at several frequencies and measured both the AM and phase noise spur amplitude. The carrier was 100 MHz and the AM depth was set to 1%. Getting a consistent AM spur above the noise floor was what I was looking for.
I then inserted the cited LA and repeated the same measurements.
Note the new noise columns that had to be added. The LA effectively eliminated the AM spur completely, reducing it to the noise floor. There is still a corresponding phase noise spur, reduced also. (Subsequent testing indicated this was incidental phase modulation from the source.) Here is a sample plot for the 100 kHz case with no intervening limiting amplifier. The phase noise window is displayed at the top and the AM noise window is displayed at the bottom. Marker 1 in each window is set at 100 kHz.
And here is a corresponding sample plot for the 100 kHz case when using the limiting amplifier. As I mentioned previously, the AM spur is eliminated which I was looking for. The corresponding phase noise spur dropped another 12 dB. For some reason, at least for this sample, the AM noise floor above 10 kHz is not flat as would be ideal.
In general, we should use a limiting amplifier if AM noise or spurs are significant with respect to phase noise. In a measurement system that can measure both, we typically want AM noise or spurs to be at least 10 dB below phase noise or spurs at the same offset frequencies. (We weren’t quite getting that in the first table above.) Ideally, the same would be true for the clock receiver accounting for its AM rejection. For example, if both the input clock’s AM noise floor and phase noise floor were the same at a particular offset frequency, then we would want the clock receiver to reject or attenuate AM noise further by 10 dB. This performance is not always specified and may need to be measured. It is also often a function of the input clock slew rate or rise/fall time. Differential Signaling A limiting amplifier is useful for removing AM from both single-ended and differential clocks. However, differential clocks are themselves an important approach to combating AM noise. One of the most important reasons for differential signaling on balanced lines is common mode (CM) noise rejection. Since most AM noise on differential signals is CM (e.g. due to power supplies) then differential receivers will tend to reject AM. This can be illustrated pictorially in the figures below. First, consider amplitude noise impressed upon a single-ended clock.
Now, consider the same amplitude noise impressed upon a differential clock.
There are several aspects to the diagram worth noting:
All of these will help to prevent CM AM noise from impacting the measurement. Unfortunately, most spectrum and phase noise analysis instruments have single-ended inputs and don’t directly support differential measurements. If we replace the receiver in the diagram with an instrument, what is the best approach? A ready measurement would be to route one differential clock polarity, e.g. CLKP, to the instrument and terminate the unmeasured polarity output, e.g. CLKN, in to 50 Ω. Generally you will want to AC-couple these so as to present roughly the same impedance. The necessity for balanced termination is discussed in Timing 101 #10: The Case of the Half-terminated Differential Output Clock. This is a valid measurement but is overly conservative as it neglects the advantage that would actually be experienced in a differential clock system. What we need is a device that will convert the differential signal to a single-ended signal. Such a device is known as a balun (taken from balanced to unbalanced). This could be in the form of an amplifier (sometimes called an active balun) or more typically a passive component. As an example of the latter, a classic transformer balun or voltage balun has a center-tapped winding on one side for converting 100 Ω differential to single-ended 50 Ω. The example balun used in these tests is the Tektronix (formerly Picosecond Pulse Labs) PSPL5310R. This is a phase matched balun which can operate from 4 MHz to 6.5 GHz. Unfortunately, for some reason, these are no longer available from Tektronix. Other vendors which sell baluns include MACOM, Marki Microwave, and Mini-Circuits. (This is not meant to be an inclusive and exhaustive list. These are just companies I am familiar with.) Look for a balun wideband enough to pass the necessary waveform with sufficient risetime and with good phase and amplitude balance. The old PSPL balun had anywhere from ± 0.5 to ± 2 degrees differential phase balance and ± 0.1 to +0.3/0.2 dB differential amplitude balance depending on the frequency range. Example DUT with AM Noise I have selected for a practical example one of my favorite “desert island” parts, the venerable Si570 which is an older generation programmable oscillator. It was the first 5 mm x 7 mm I2C programmable oscillator that could cover 10 MHz to 1.4 GHz. Radio amateurs may recognize this device as used in some “Softrock” SDR (Software Defined Radio) applications. Not only can it support such a wide frequency range but it can also be ordered with “real” LVPECL drivers. By this I mean it can drive DC-coupled LVPECL loads defined as 50 Ω terminated in to VDD – 2V. (By contrast, clock devices typically provide LVPECL compatible modes where they can supply the right swing when AC-coupled.) There is some CM (Common Mode) AM noise using this mode. However, this is mitigated when used differentially as intended. Below we will tabulate several measurement scenarios with and without a balun and LA. The DUT is an evaluation board with P/N 570AAA000121DG installed operating AC-coupled. This is a differential programmable XO with a 100 MHz starting frequency, output format 3.3V LVPECL. Here are the phase jitter results for various configurations.
The biggest bang for the buck so to speak was using a balun. That got us to the 300fs range or less which is what we expect this device to yield. (The closest Si570 datasheet spec is 360 fs typical for Fout from 125 to 500 MHz.) Here are a few plots to go with this table. First, the single-ended configuration with the highest phase jitter, over 600 fs. Note the several spurs above 1 MHz in both the AM and phase noise measurement windows.
Next is the balun only configuration which eliminates some spurs and drops the phase jitter roughly in half, i.e. below 300 fs.
Finally, here is the phase noise plot combining the DUT driving the LA differentially which in turn drives the balun connected to the E5052B. This plot eliminates all the spurs above 1 MHz and still keeps the phase noise floor mostly below -150 dBc/Hz beyond this offset frequency.
Virtual Limiting Amplifier Ignoring spurs, it is possible in principle to estimate the DUT’s post-LA phase noise performance by mathematically applying a “virtual limiting amplifier”, if you know what the LA AM noise floor will be and what the AM to PM conversion is for your instrument. However, that is a topic for another time. In practice, as one peels the onion to achieve lower and lower phase noise measurements, spurs play an increasingly larger role. This can be problematic for estimation purposes since even if the location of spurs can be predicted, often their amplitudes cannot. A Few Rules of Thumb Based on this and the previous Timing 201 post, here are a few suggested rules of thumb when making phase noise measurements on sources that may have AM noise:
Having a good limiting amplifier and a good balun on your bench can help you make more accurate phase noise and jitter measurements, and help distinguish the type of noise contributors you are dealing with. If you are working with differential clocks, you really should use a balun even if AM noise is not that significant. Conclusion I hope you have enjoyed this Timing 201 article. If you have a favorite balun or limiting amplifier you would like to share with others, please let me know. As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words “Timing 201” in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on. Cheers, Kevin |
Sep 26 2019, 7:57 PM |
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kgsmith
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Selected an answer for Cannot set reference frequency over 54MHz in ClockBuilder Pro v2.35 Show more |
Aug 14 2019, 3:37 PM |
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kgsmith
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Updated
Timing 201 #1: The Case of the Phase Noise That Wasn't - Part 1 on Blog
Introduction Hello and welcome to the inaugural article for a new blog series, Timing 201. My previous blog series, Timing 101, ran for 12 articles over a period of roughly a year and a half. As the name suggests, I intend to discuss timing topics with a little bit more breadth and depth than might be considered “Timing 101” material. However, that does not mean I won’t cover introductory material, if and when it’s called for, especially if readers ask for it. When More is Less You may recall that clock buffers are typically specified in terms of additive jitter. That is because they do not have an intrinsic phase noise source such as an XO (crystal oscillator) or a PLL’s VCXO. They consist of only amplifiers and perhaps dividers. So we would generally expect an XO followed by a clock buffer to have at least somewhat increased phase noise or jitter compared to the XO alone. All things being equal, this will be the case, except when the amplifier has sufficiently high gain to act as a limiting amplifier or LA. In these situations, the apparent measured source + LA phase noise may actually decrease. I ran in to this phenomena years ago evaluating various clock + buffer combinations. The results weren’t always making sense and it turned out at the time that some of the noise I was measuring was in fact, not really phase noise, hence the title of this case. To see how this might happen, let’s touch on what is meant here by apparent measured phase noise. Phasors ON You may recall I discussed modulation spurs previously in Timing 101 #7: The Case of the Spurious Phase Noise Part II. In that article, I considered carriers with relatively small amounts of AM (Amplitude Modulation) and narrowband FM (Frequency Modulation) or equivalent PM (Phase Modulation). The general ideas comparing AM and FM/PM spurs also apply to AM and FM/PM noise. One topic I did not touch on at that time was the phasor or phase vector representations of AM and NB FM as shown below. The carrier vector is shown as a thick red arrow and the modulation LSB (lower sideband) and USB (upper sideband) vector components are shown as thinner blue arrows. The vector sum or resultant of the modulation is the thick blue arrow. The modulating frequency is f<subscript>M and the rotating arrows indicate the change in the modulation vectors over time versus the carrier. For the figures below the overall vector sum is the geometric addition of the carrier + modulation resultant.
What’s useful about the phasor representation is that it indicates that random noise modulating the carrier can be regarded as consisting of both AM and PM components. That is, components of the noise contributing to carrier magnitude changes are the AM components. Likewise, components of the noise contributing to carrier angle changes are FM or equivalent PM components. You may see authors emphasizing this distinction by using script L(f) or ℒ(f) to refer to PM noise or “real” phase noise and script M(f) or ℳ(f) to refer to AM noise. The first paper I know of using this notation is: Spectral Density Analysis: Frequency Domain Specification and Measurement of Signal Stability, by Donald Halford, John H. Shoaf, and A. S. Risley, National Bureau of Standards, Boulder, CO, published in 27th Annual Symposium on Frequency Control, 12-14 June 1973, https://tf.nist.gov/general/pdf/1558.pdf The magnitude of noise that is AM + PM will be the RSS or Root Sum Square of the individual modulation contributions. Instruments that treat these noise components the same will then “see” this RSS noise directly as phase noise. This is what is meant by apparent phase noise and it is a particular issue for Spectrum Analyzers as discussed below. The Spectrum Analyzer in Brief As I noted in Timing 101 #7, Spectrum Analyzers do not preserve phase information and so a low modulation AM spur appears similar to a narrow band low modulation FM spur. Below is a block diagram for a classic swept spectrum analyzer which suggests why. It is essentially a calibrated frequency selective peak responding voltmeter. The difference in phase between the DUT (Device Under Test) and the LO (Local Oscillator) inputs at the mixer is arbitrary. The Spectrum Analyzer doesn’t “know” anything about their relative phases and AM and PM cannot be distinguished.
The Phase Noise Analyzer in Brief By contrast, the Phase Noise Analyzer is much less susceptible to AM. The simplified block diagram below gives the basic idea behind the method typically used by Phase Noise Analyzers and Signal Source Analyzers. The mixer is usually a double-balanced mixer to suppress even-order mixing products.
Note that, unlike the Spectrum Analyzer, there is a PLL (Phase Lock Loop) that enforces a specific phase relationship between the DUT and the Reference. Further, it can be shown that AM and PM can be distinguished as follows.
As designed, the Phase Noise Analyzer will be superior to the spectrum analyzer for rejecting AM. Take It to the Limit So how exactly does the limiting amplifier or LA help us here? The clue lies in the behavior of the LA: It removes, or at least minimizes, amplitude variation from the clock signal. Therefore, if a source has both AM and PM noise components, then an ideal limiter will remove the AM component noise leaving only the PM noise (the genuine phase noise) behind. The exaggerated sketch below gives the basic idea.
Now getting back to the original work which prompted this post: If a clock source had apparent phase noise that included both AM and PM noise contributions, then following it with a high gain clock buffer or LA would strip away the AM resulting in less than expected measured phase noise. Rather than yielding additive jitter the new component apparently yielded “subtractive” jitter. Thus the case of the phase noise that wasn’t. When should AM be considered when making phase noise measurements? The short answer is that AM is always a potential consideration when one is making careful jitter and phase noise measurements. Having a limiter on one’s lab bench is as important as a balun. However, there are specific instances where AM can be more of an issue than others. 1. Measuring phase noise using a spectrum analyzer or any other instrument that does not sufficiently reject AM. A limiter can be valuable even when working with a Phase Noise Analyzer by suppressing AM beyond the rejection capability of the mixer. This may be necessary when measuring very low phase noise sources. 2. Measuring low frequency low phase noise sources. You may recall the 20log(N) rule, i.e. if the carrier frequency of a clock is divided down by a factor of N then we expect the phase noise to decrease by 20log(N); however, this rule only applies to phase noise. If there is significant AM noise also then this component will loom larger, as we decrease the carrier frequency, and potentially impact measurements. 3. Measuring a source known or suspected to have AM noise. Clock sources with high common mode noise fall in to this category. For example, we specifically inject power supply ripple when testing oscillator power supply rejection. This is why you see a limiting amplifier shown in Figure 5. PSRR Setup in AN491: Power Supply Rejection For Low-Jitter Clocks. See the highlighted block in the diagram below which comes from that app note.
4. Troubleshooting Finally, the ability to distinguish between phase noise and spurs, and AM noise and spurs, can be very helpful when troubleshooting a system and determining the root cause of performance issues. Additional testing may also be needed to determine how sensitive the ultimate receiver is to clock impairments that include AM noise. Conclusion I hope you have enjoyed this Timing 201 article. In the next article, I will give some measurement examples and offer a few rules of thumb. As always, if you have topic suggestions for this blog or timing-related questions, please send them to kevin.smith@silabs.com with “Timing 201” in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on. Cheers, Kevin
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Jun 27 2019, 5:17 PM |
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kgsmith
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Updated
Timing 201 #1: The Case of the Phase Noise That Wasn't - Part 1 on Blog
Introduction Hello and welcome to the inaugural article for a new blog series, Timing 201. My previous blog series, Timing 101, ran for 12 articles over a period of roughly a year and a half. As the name suggests, I intend to discuss timing topics with a little bit more breadth and depth than might be considered “Timing 101” material. However, that does not mean I won’t cover introductory material, if and when it’s called for, especially if readers ask for it. When More is Less You may recall that clock buffers are typically specified in terms of additive jitter. That is because they do not have an intrinsic phase noise source such as an XO (crystal oscillator) or a PLL’s VCXO. They consist of only amplifiers and perhaps dividers. So we would generally expect an XO followed by a clock buffer to have at least somewhat increased phase noise or jitter compared to the XO alone. All things being equal, this will be the case, except when the amplifier has sufficiently high gain to act as a limiting amplifier or LA. In these situations, the apparent measured source + LA phase noise may actually decrease. I ran in to this phenomena years ago evaluating various clock + buffer combinations. The results weren’t always making sense and it turned out at the time that some of the noise I was measuring was in fact, not really phase noise, hence the title of this case. To see how this might happen, let’s touch on what is meant here by apparent measured phase noise. Phasors ON You may recall I discussed modulation spurs previously in Timing 101 #7: The Case of the Spurious Phase Noise Part II. In that article, I considered carriers with relatively small amounts of AM (Amplitude Modulation) and narrowband FM (Frequency Modulation) or equivalent PM (Phase Modulation). The general ideas comparing AM and FM/PM spurs also apply to AM and FM/PM noise. One topic I did not touch on at that time was the phasor or phase vector representations of AM and NB FM as shown below. The carrier vector is shown as a thick red arrow and the modulation LSB (lower sideband) and USB (upper sideband) vector components are shown as thinner blue arrows. The vector sum or resultant of the modulation is the thick blue arrow. The modulating frequency is f<subscript>M and the rotating arrows indicate the change in the modulation vectors over time versus the carrier. For the figures below the overall vector sum is the geometric addition of the carrier + modulation resultant.
What’s useful about the phasor representation is that it indicates that random noise modulating the carrier can be regarded as consisting of both AM and PM components. That is, components of the noise contributing to carrier magnitude changes are the AM components. Likewise, components of the noise contributing to carrier angle changes are FM or equivalent PM components. You may see authors emphasizing this distinction by using script L(f) or ℒ(f) to refer to PM noise or “real” phase noise and script M(f) or ℳ(f) to refer to AM noise. The first paper I know of using this notation is: Spectral Density Analysis: Frequency Domain Specification and Measurement of Signal Stability, by Donald Halford, John H. Shoaf, and A. S. Risley, National Bureau of Standards, Boulder, CO, published in 27th Annual Symposium on Frequency Control, 12-14 June 1973, https://tf.nist.gov/general/pdf/1558.pdf The magnitude of noise that is AM + PM will be the RSS or Root Sum Square of the individual modulation contributions. Instruments that treat these noise components the same will then “see” this RSS noise directly as phase noise. This is what is meant by apparent phase noise and it is a particular issue for Spectrum Analyzers as discussed below. The Spectrum Analyzer in Brief As I noted in Timing 101 #7, Spectrum Analyzers do not preserve phase information and so a low modulation AM spur appears similar to a narrow band low modulation FM spur. Below is a block diagram for a classic swept spectrum analyzer which suggests why. It is essentially a calibrated frequency selective peak responding voltmeter. The difference in phase between the DUT (Device Under Test) and the LO (Local Oscillator) inputs at the mixer is arbitrary. The Spectrum Analyzer doesn’t “know” anything about their relative phases and AM and PM cannot be distinguished.
The Phase Noise Analyzer in Brief By contrast, the Phase Noise Analyzer is much less susceptible to AM. The simplified block diagram below gives the basic idea behind the method typically used by Phase Noise Analyzers and Signal Source Analyzers. The mixer is usually a double-balanced mixer to suppress even-order mixing products.
Note that, unlike the Spectrum Analyzer, there is a PLL (Phase Lock Loop) that enforces a specific phase relationship between the DUT and the Reference. Further, it can be shown that AM and PM can be distinguished as follows.
As designed, the Phase Noise Analyzer will be superior to the spectrum analyzer for rejecting AM. Take It to the Limit So how exactly does the limiting amplifier or LA help us here? The clue lies in the behavior of the LA: It removes, or at least minimizes, amplitude variation from the clock signal. Therefore, if a source has both AM and PM noise components, then an ideal limiter will remove the AM component noise leaving only the PM noise (the genuine phase noise) behind. The exaggerated sketch below gives the basic idea.
Now getting back to the original work which prompted this post: If a clock source had apparent phase noise that included both AM and PM noise contributions, then following it with a high gain clock buffer or LA would strip away the AM resulting in less than expected measured phase noise. Rather than yielding additive jitter the new component apparently yielded “subtractive” jitter. Thus the case of the phase noise that wasn’t. When should AM be considered when making phase noise measurements? The short answer is that AM is always a potential consideration when one is making careful jitter and phase noise measurements. Having a limiter on one’s lab bench is as important as a balun. However, there are specific instances where AM can be more of an issue than others. 1. Measuring phase noise using a spectrum analyzer or any other instrument that does not sufficiently reject AM. A limiter can be valuable even when working with a Phase Noise Analyzer by suppressing AM beyond the rejection capability of the mixer. This may be necessary when measuring very low phase noise sources. 2. Measuring low frequency low phase noise sources. You may recall the 20log(N) rule, i.e. if the carrier frequency of a clock is divided down by a factor of N then we expect the phase noise to decrease by 20log(N); however, this rule only applies to phase noise. If there is significant AM noise also then this component will loom larger, as we decrease the carrier frequency, and potentially impact measurements. 3. Measuring a source known or suspected to have AM noise. Clock sources with high common mode noise fall in to this category. For example, we specifically inject power supply ripple when testing oscillator power supply rejection. This is why you see a limiting amplifier shown in Figure 5. PSRR Setup in AN491: Power Supply Rejection For Low-Jitter Clocks. See the highlighted block in the diagram below which comes from that app note.
4. Troubleshooting Finally, the ability to distinguish between phase noise and spurs, and AM noise and spurs, can be very helpful when troubleshooting a system and determining the root cause of performance issues. Additional testing may also be needed to determine how sensitive the ultimate receiver is to clock impairments that include AM noise. Conclusion I hope you have enjoyed this Timing 201 article. In the next article, I will give some measurement examples and offer a few rules of thumb. As always, if you have topic suggestions for this blog or timing-related questions, please send them to kevin.smith@silabs.com with “Timing 201” in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on. Cheers, Kevin
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Jun 27 2019, 5:16 PM |
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