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kgsmith
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Timing 201 #6: The Case of the Autonomously Resetting Clock Generator on Blog
Introduction Some five years ago, a customer contacted us thinking they needed to return a clock generator device that would often go into a continuously resetting state after power-up. We had never heard of such unusual behavior and wondered if there was anything wrong with this particular unit’s POR (Power On Reset) circuit. Fortunately, the customer had a small PC board that frequently exhibited the behavior, and which they could ship to us for troubleshooting in our lab. This enabled us to more quickly determine the root cause and verify the solution. It turned out that an overlooked spec for a passive component located elsewhere on the board was causing large consequences for the customer’s application. The lessons learned are generally applicable and the subject of this blog article, The Case of the Autonomously Resetting Clock Generator.
BLUF (Bottom Line Up Front) The clock generator’s POR circuit was not at fault. In fact, it was behaving exactly as it should. Rather, an external 3.3 V regulator circuit was marginally stable. Oscillations on the 3.3 V rail could be sufficiently large to trigger autonomous resets.
Browsing the Power Supply Voltages The customer board took in +12 V and regulated this down to the +3.3 V and +1.8 V rails required by the Si5341 clock generator. I used a lab power supply with pushbutton Output On/Off to provide the necessary +12 V input. This allowed me to manually and conveniently power cycle many times in order to observe and contrast a passing versus failing (continuously resetting) power-up event. The series of oscilloscope screen captures below display the 3.3 V (orange trace) at the top and the 1.8 V (blue trace) at the bottom. The figure below shows the nominally settled behavior of the 3.3 V and 1.8 V after a failed power-up. The 1.8 V supply is completely accurate. However, the 3.3 V supply is clearly oscillating and even periodically dropping down to about 2.4 V, far below the POR trip threshold.
What about those occasions where the part successfully powers up? Per the figure below, both the 3.3 V and 1.8 V rails are at their nominal targets but the 3.3 V supply appears much noisier. This is another clue that the 3.3 V regulator circuit may be marginally stable.
I then looked at the start-up behavior. When the device fails, the 3.3 V supply starts oscillating straight away.
Even when the unit successfully powers up, as depicted below, the 3.3 V supply exhibits overshoot before settling down to a noisy nominal voltage.
An Informative Vendor Data Sheet The customer was using a 500 mA LDO (Low Drop Out) regulator in a SOT-23-5 package. Reading the vendor’s data sheet, I noticed that the typical application drawing showed the output capacitor as a 2.2 uF tantalum. Further, the data sheet explicitly stated that the output capacitor needed an ESR of about 1 Ω and that ultra-low ESR caps could cause oscillation. Inspecting the output cap on the customer’s board revealed that it was a ceramic capacitor. These can have an ESR with an order of magnitude less than an electrolytic capacitor. So that suggested the next experiment to try.
Demonstrating the Fix We hacked in a 1 Ω resistor in series with the ceramic capacitor in order to emulate the approximate ESR of a tantalum capacitor. A close-up photo of the hack is shown below. The brown component in the upper part of the “elbow” is the existing capacitor. The component marked “01Y” is the 1 Ω resistor.
The hack was ugly but effective:
As the resulting screen cap shows above, the 3.3 V supply is much less noisy and the start-up transient is very small and quickly damped out. After many attempts, no autonomous resets were observed, current draw was as expected, and the device always yielded output clocks. This outcome was good enough for the customer to take over and do additional verification testing for their particular application.
Some Lessons Learned This Timing 201 case exemplifies several lessons learned. These are listed below, going from the general to the specific.
Conclusion I hope you have enjoyed this Timing 201 article. As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on. Cheers, |
Jun 10 2020, 8:57 PM |
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kgsmith
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Updated
Timing 201 #6: The Case of the Autonomously Resetting Clock Generator on Blog
Introduction Some five years ago, a customer contacted us thinking they needed to return a clock generator device that would often go into a continuously resetting state after power-up. We had never heard of such unusual behavior and wondered if there was anything wrong with this particular unit’s POR (Power On Reset) circuit. Fortunately, the customer had a small PC board that frequently exhibited the behavior, and which they could ship to us for troubleshooting in our lab. This enabled us to more quickly determine the root cause and verify the solution. It turned out that an overlooked spec for a passive component located elsewhere on the board was causing large consequences for the customer’s application. The lessons learned are generally applicable and the subject of this blog article, The Case of the Autonomously Resetting Clock Generator.
BLUF (Bottom Line Up Front) The clock generator’s POR circuit was not at fault. In fact, it was behaving exactly as it should. Rather, an external 3.3 V regulator circuit was marginally stable. Oscillations on the 3.3 V rail could be sufficiently large to trigger autonomous resets.
Browsing the Power Supply Voltages The customer board took in +12 V and regulated this down to the +3.3 V and +1.8 V rails required by the Si5341 clock generator. I used a lab power supply with pushbutton Output On/Off to provide the necessary +12 V input. This allowed me to manually and conveniently power cycle many times in order to observe and contrast a passing versus failing (continuously resetting) power-up event. The series of oscilloscope screen captures below display the 3.3 V (orange trace) at the top and the 1.8 V (blue trace) at the bottom. The figure below shows the nominally settled behavior of the 3.3 V and 1.8 V after a failed power-up. The 1.8 V supply is completely accurate. However, the 3.3 V supply is clearly oscillating and even periodically dropping down to about 2.4 V, far below the POR trip threshold.
What about those occasions where the part successfully powers up? Per the figure below, both the 3.3 V and 1.8 V rails are at their nominal targets but the 3.3 V supply appears much noisier. This is another clue that the 3.3 V regulator circuit may be marginally stable.
I then looked at the start-up behavior. When the device fails, the 3.3 V supply starts oscillating straight away.
Even when the unit successfully powers up, as depicted below, the 3.3 V supply exhibits overshoot before settling down to a noisy nominal voltage.
An Informative Vendor Data Sheet The customer was using a 500 mA LDO (Low Drop Out) regulator in a SOT-23-5 package. Reading the vendor’s data sheet, I noticed that the typical application drawing showed the output capacitor as a 2.2 uF tantalum. Further, the data sheet explicitly stated that the output capacitor needed an ESR of about 1 Ω and that ultra-low ESR caps could cause oscillation. Inspecting the output cap on the customer’s board revealed that it was a ceramic capacitor. These can have an ESR with an order of magnitude less than an electrolytic capacitor. So that suggested the next experiment to try.
Demonstrating the Fix We hacked in a 1 Ω resistor in series with the ceramic capacitor in order to emulate the approximate ESR of a tantalum capacitor. A close-up photo of the hack is shown below. The brown component in the upper part of the “elbow” is the existing capacitor. The component marked “01Y” is the 1 Ω resistor.
The hack was ugly but effective:
As the resulting screen cap shows above, the 3.3 V supply is much less noisy and the start-up transient is very small and quickly damped out. After many attempts, no autonomous resets were observed, current draw was as expected, and the device always yielded output clocks. This outcome was good enough for the customer to take over and do additional verification testing for their particular application.
Some Lessons Learned This Timing 201 case exemplifies several lessons learned. These are listed below, going from the general to the specific.
Conclusion I hope you have enjoyed this Timing 201 article. As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on. Cheers, |
Jun 10 2020, 5:11 PM |
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kgsmith
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Posted
Timing 201 #6: The Case of the Autonomously Resetting Clock Generator on Blog
Introduction Some five years ago, a customer contacted us thinking they needed to return a clock generator device that would often go into a continuously resetting state after power-up. We had never heard of such unusual behavior and wondered if there was anything wrong with this particular unit’s POR (Power On Reset) circuit. Fortunately, the customer had a small PC board that frequently exhibited the behavior, and which they could ship to us for troubleshooting in our lab. This enabled us to more quickly determine the root cause and verify the solution. It turned out that an overlooked spec for a passive component located elsewhere on the board was causing large consequences for the customer’s application. The lessons learned are generally applicable and the subject of this blog article, The Case of the Autonomously Resetting Clock Generator.
BLUF (Bottom Line Up Front) The clock generator’s POR circuit was not at fault. In fact, it was behaving exactly as it should. Rather, an external 3.3 V regulator circuit was marginally stable. Oscillations on the 3.3 V rail could be sufficiently large to trigger autonomous resets.
Browsing the Power Supply Voltages The customer board took in +12 V and regulated this down to the +3.3 V and +1.8 V rails required by the Si5341 clock generator. I used a lab power supply with pushbutton Output On/Off to provide the necessary +12 V input. This allowed me to manually and conveniently power cycle many times in order to observe and contrast a passing versus failing (continuously resetting) power-up event. The series of oscilloscope screen captures below display the 3.3 V (orange trace) at the top and the 1.8 V (blue trace) at the bottom. The figure below shows the nominally settled behavior of the 3.3 V and 1.8 V after a failed power-up. The 1.8 V supply is completely accurate. However, the 3.3 V supply is clearly oscillating and even periodically dropping down to about 2.4 V, far below the POR trip threshold.
What about those occasions where the part successfully powers up? Per the figure below, both the 3.3 V and 1.8 V rails are at their nominal targets but the 3.3 V supply appears much noisier. This is another clue that the 3.3 V regulator circuit may be marginally stable.
I then looked at the start-up behavior. When the device fails, the 3.3 V supply starts oscillating straight away.
Even when the unit successfully powers up, as depicted below, the 3.3 V supply exhibits overshoot before settling down to a noisy nominal voltage.
An Informative Vendor Data Sheet The customer was using a 500 mA LDO (Low Drop Out) regulator in a SOT-23-5 package. Reading the vendor’s data sheet, I noticed that the typical application drawing showed the output capacitor as a 2.2 uF tantalum. Further, the data sheet explicitly stated that the output capacitor needed an ESR of about 1 Ω and that ultra-low ESR caps could cause oscillation. Inspecting the output cap on the customer’s board revealed that it was a ceramic capacitor. These can have an ESR with an order of magnitude less than an electrolytic capacitor. So that suggested the next experiment to try.
Demonstrating the Fix We hacked in a 1 Ω resistor in series with the ceramic capacitor in order to emulate the approximate ESR of a tantalum capacitor. A close-up photo of the hack is shown below. The brown component in the upper part of the “elbow” is the existing capacitor. The component marked “01Y” is the 1 Ω resistor.
The hack was ugly but effective:
As the resulting screen cap shows above, the 3.3 V supply is much less noisy and the start-up transient is very small and quickly damped out. After many attempts, no autonomous resets were observed, current draw was as expected, and the device always yielded output clocks. This outcome was good enough for the customer to take over and do additional verification testing for their particular application.
Some Lessons Learned This Timing 201 case exemplifies several lessons learned. These are listed below, going from the general to the specific.
Conclusion I hope you have enjoyed this Timing 201 article. As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on. Cheers, |
Jun 09 2020, 8:38 PM |
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kgsmith
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Posted
Timing 201 #5: The Case of the Parasitic PLL - Part 3 on Blog
Introduction As I write this, many of us around the world are working under COVID-19 quarantine conditions. So before diving in, I want to wish all of you and yours the very best of health. Please take care of yourselves out there! Now to recap so far:
ILBW (Injection Lock Bandwidth) The figure below was presented in Part 1 and follows Wolaver’s development culminating in this equation with the important takeaways noted.
Wolaver treated the injection constant or gain KINJ as the injection lock range. It is useful to think of this lock range as the Injection Lock Bandwidth or ILBW to contrast it with the PLL’s loop bandwidth BW. In order to minimize the risk of injection locking we want ILBW < BW In fact, we would prefer for ILBW << BW. A practical empirical rule of thumb we have applied is the following ILBW <= 0.3 * BW We will apply this rule of thumb in later example calculations.
ILBW Practical Issues Let’s take another look at Wolaver’s equation for KINJ as the injection lock range aka the Injection Lock Bandwidth or ILBW. In the annotated figure below I call out some practical issues.
There are several difficulties that may arise when attempting to make direct calculations of this equation based on measurements of the individual factors:
Provided one can apply a calibrated high frequency interferer, it is often easier to measure the effective ILBW. The rest of this post will discuss a couple of ideas on how to do this.
ILBW Measurement Approaches This post will discuss two different measurement approaches summarized in the table below. The first method applies an asynchronous aggressor source and uses the offset spur result measured on a spectrum analyzer to estimate the ILBW. The second method applies a synchronous aggressor source and measures the ILBW directly from a phase noise analyzer.
These methods will be demonstrated using older simpler architecture devices where injection may be conveniently observed. Modern clock devices are generally less susceptible to injection due to architecture, shielding, etc. The examples that follow will give an indication of what you might observe with classic narrow bandwidth single loop PLLs.
PLL Injection Sensitivity – Estimating ILBW via Asynchronous Injection Using this first approach, we measure the spur that results on the output for a given asynchronous but near-synchronous injection applied to the device. The general idea is to configure the DUT as typical, using an input clock source that does not have significant harmonics at or near the PLL’s VCO frequency. Then apply an interferer or aggressor clock set near the VCO frequency to individual pins and determine the worst case. The general test set-up used years ago for the Si53xx SONET devices was as follows:
A general comment about probes: One can measure the voltage at device pins using a divide-by-10 high impedance differential probe, even if not specified to operate at the intended frequency, if carefully calibrated. Back when this data was collected the probes available had a 20 dB calibrated loss at 2.5 GHz. So for a -20 dBm interferer we would expect a signal at the device pins as follows assuming no additional losses. -20 dBm applied interferer How can we use this technique to estimate the ILBW or Injection Lock Bandwidth? Here are the steps.
PLL Injection Sensitivity – Example Estimated ILBW Calculations The figure below shows the spectrum for an Si53xx SONET clock device configured for an output of 622.08 MHz together with the resulting injected spur. The DUT used a post VCO output divider N = 4 to yield output frequency f0 = 622.08 MHz. For this device, the DUT VCO frequency or ftank = 622.08 MHz x 4 = 2.48832 GHz.
Here are the example calculations in this instance:
The minimum operating BW for this part is 800 Hz. Applying the rule of thumb ILBW is much less than 0.3 * 800 Hz or 240 Hz. Therefore we do not expect injection lock to be an issue. Another way of looking at the problem is to ask: For a given loop BW selection how large a spur, referred to the tank frequency, am I allowed to have using the rule of thumb? Pspur_tank (max allowed) = 20*log10(fILBW/foffset) dBc Using the same example situation as before: Pspur_tank (max allowed) = 20*log10(0.3*800/20000) dBc
Injection Lock Tolerance We can apply the information described above, together with worst case pin data, to estimate how much interfering signal the device pins can tolerate before injection lock may cause jitter to be an issue. The worst case data suggested that the interferer amplitude at a pin may be as low as –50 dBm and yield a spur as high as –44 dBc. Using this worst case pin assumption, then the worst case spur at the tank would be: Pspur_tank_wc = -44 dBc + 20*log10(4) = -44 dBc + 12 dB = -32 dBc Recall that the Pspur_tank (max allowed) for an 800 Hz BW is -38.4 dBc and so we must decrease the allowable interferer signal strength at the pins to –50 dBm – (38.4-32) = -56.4 dBm. As a practical matter, we should then decrease this by at least another 6 dB to add margin. This suggests the following criterion for the Si53xx clock chips: The interferer strength at a device pin should not exceed –62 dBm. This conservative criterion means that Si53xx clock devices should not injection lock unless an extraneous 2.5 GHz source can inject a signal > –62 dBm at an individual pin. What if we had an especially noisy application where this limit was exceeded? If significant interfering energy is present, filtering, attenuation, and good layout can reduce the level of conducted interference on sensitive pins.
PLL Injection Sensitivity – Measuring ILBW via Synchronous Injection In this second approach, we apply a synchronous interferer and observe the impact of injection lock directly on the phase noise plot. The figure below illustrates the basic idea.
Engineers who are familiar with phase noise plots will recognize that the injection locked oscillator phase noise truly looks “locked” just as if it was in a designed PLL, and not in an incidental or parasitic counterpart.
Evaluation Board Experiments Setup To demonstrate the phase noise analyzer approach, I used an RF Synthesizer evaluation board which has convenient VCO frequencies for my purposes. The figure below summarizes the test set-up. In this case however, I did not want to use a purpose-built board or inject an interfering signal at all the pins. Instead, I decided to simply remove the bypass caps and inject the synchronous interferer directly in to the power supply. You can think of this as a high frequency extension to PSRR or Power Supply Rejection Ratio testing. In other words a sort of IPRR or Injection Pulling Rejection Ratio test.
Here are the main points:
Evaluation Board Experiments Phase Noise Plots The phase noise plots below were based on data measured on an old Agilent (now Keysight) JS-500 rack system which is an E5500 superset. One of the features that’s nice about this older equipment is that the user has direct access to the measurement PLL’s loop BW. This allows one to measure very noisy and even open loop phase noise plots.
You can read the ILBW directly from the intersection of the locked phase noise plots versus the open loop phase noise plot. As suggested by the Wolaver equation, increasing the power of the injected signal results in a wider ILBW which would restrict the loop bandwidths at which the device would operate. In these experiments, ILBW only approached 10 kHz even with a +10 dBm synchronous signal injected in to the power supply. Note that the Si4133 is not operated as a jitter attenuator but rather as a clock generator with a good quality TCXO as the reference source or input clock and a typical operating bandwidth ≈ 200 kHz.
Estimated versus Measured ILBW In the 2009 ACISC paper in the references, I compared both methods applied to the RF Synthesizer and obtained good agreement. See the figure below comparing ILBW as estimated based on 1 MHz offsets versus direct measurement.
Injection Lock Troubleshooting Injection lock may be an issue if the device’s clock output jitter is out of spec, cannot be accounted for given the input clock’s phase noise, and the device’s Jitter Transfer Function, and exhibits an unexpected jitter distribution. A suspicious example of the latter would be a bimodal jitter distribution. A general troubleshooting procedure is listed below. Try each of these items in turn and check to see if the situation improves.
In the particular case of Si53xx clock ICs, application note AN59 describes generally good layout and filtering practices.
Summary In this and the previous related blog posts, I have reviewed injection pulling and lock, injection mitigation, and practical measurements. Here are the main points to sum up:
References The same references that applied to the previous posts apply here. They are repeated again below for convenience. Some of the material covered here was presented at the Austin Conference on Integrated Systems and Circuits (ACISC) in 2009. If you are interested, you can email me to request a copy of the paper “Practical Issues Measuring and Minimizing Injection Pulling in Board-level Oscillator and PLL Applications” and accompanying slides. As mentioned previously, the best practical overall book treatment I am familiar with is in Wolaver’s text:
This is a slim volume for a PLL book but it punches well above its weight in terms of information.
Here are several foundational papers worth reading on the topic of injection.
If you have favorite references you would like to share, please pass them along to me.
Conclusion I hope you have enjoyed this Timing 201 series on injection lock. As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on. Cheers,
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Apr 25 2020, 12:17 AM |
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kgsmith
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Updated
Timing 201 #4: The Case of the Parasitic PLL - Part 2 on Blog
Introduction In the last Timing 201 post, I discussed the parasitic Phase-Locked Loop (PLL) in which an independent oscillator can couple energy in to a PLL’s VCO so as to influence or even take over the PLL’s output frequency and phase. I then reviewed some basic injection theory, including the concept of injection lock range. Given the amount of material I would like to cover, I am going to follow-up that post with two more articles. This installment, Part 2, will discuss how to minimize injection sensitivity generally. Part 3, to come later, will cover the topic of measuring injection sensitivity. A Brief Review Per the last article, injection pulling or locking refers to when one independent oscillator disturbs or locks the frequency and phase of another independent near-synchronous oscillator. We then reviewed injection theory after Wolaver (1991) culminating in this equation with the important take-aways noted.
ILBW (Injection Lock Bandwidth) Wolaver treated the injection constant or gain KINJ as the injection lock range. It is useful to regard this lock range as the Injection Lock Bandwidth (ILBW) to contrast it with the PLL’s loop bandwidth (BW). From here on, I will use this nomenclature. The bottom line is that, in order to minimize the risk of injection locking, we want BW > ILBW. Ideally, BW would be significantly greater than the PLL’s ILBW. The factors in the formula suggest where we might run in to trouble. For example, LC tank oscillators, especially when integrated, have much lower Q compared to crystal oscillators. Further, the trend is for higher and higher frequency clocks. The resonant tank frequency itself is usually dictated by something on the order of 2 times the maximum 50% duty cycle output clock frequency we would like to support. So we should be on guard for this issue when considering narrow band (NB) and high frequency low-Q VCO tank circuit PLLs. So why don’t we routinely run in to injection problems today? Well you still can, if you are rolling your own NB discrete synchronous PLLs and especially if you co-locate them. This article series is in part an attempt to warn you of some possible concerns. Board and IC designers have learned over the years to adopt injection resistant practices and PLL topologies. First, let’s begin by considering some typical injection mechanisms. Injection Mechanisms There are several common injection mechanisms in which aggressor oscillator noise may couple in to a tank oscillator circuit. The first two listed are suggested by the figure below:
We can mitigate, or reduce the impact, of injection by directly addressing these injection mechanisms and/or by using more injection resistant system-level approaches. Injection Mitigation via Good EMC Design Injection can be regarded as a special topic within the field of EMC (Electromagnetic Compatibility). We can minimize injection noise power applied at the tank for each of these mechanisms using good practices for designers cognizant of general Electromagnetic Interference (EMI) issues.
All of the above methods attack the problem by reducing the strength of the aggressor noise PINJ. However, in addition to these direct approaches, there are some other more systemic ways of minimizing injection problems. Injection Mitigation via Thoughtful Frequency Planning You may recall that I mentioned the general problem of injection pulling and locking arises when working with signals and oscillators that are synchronous or nearly so. What do I mean by nearly-synchronous? A SONET application board with lots of clock I/O all running at or near SONET frequencies within a few ppm of each other is a classic example. One approach, if you have multiple PLLs or clock devices co-located on the same printed circuit board, is to configure them so that the VCO frequencies are asynchronous from each other. For example, consider an application where you have two adjacent Si570 I2C-Programmable XOs on a PCB. You can minimize the risk of injection crosstalk (XTALK) by configuring the devices so that their internal DCOs or Digitally Controlled Oscillators are well off frequency from each other. Consider the Si570 Detailed Block Diagram below taken from this datasheet. In the diagram, HS_DIV refers to the DCO High Speed Divider with possible values [4-7, 9, 11]. N1 is the CLKOUT Output Divider with allowed values [1] and [2, 4, 6, …, 27]. Finally, the datasheet constrains the DCO frequency to 4.850 GHz £ fosc £ 5.67 GHz. Given these constraints, there can often be multiple frequency plan solutions that output the same clock frequency.
For example, the DCOs can be made significantly asynchronous even when the output clocks are identical in frequency. Here are two valid Si570 configurations that both yield f1 = 155.52 MHz outputs.
In this instance, each DCO frequency is asynchronous, greatly minimizing the risk of injection XTALK. Injection Mitigation via Beneficial Clock Architectures One architectural approach is to simply minimize the number of PLLs, and therefore VCOs, with associated tank circuits, that might be susceptible to injection XTALK. An example clock generator that minimizes the number of PLLs is the Si5338 I2C-Programmable Any-Frequency, Any-Output Quad Clock Generator. The functional block diagram below is taken from the Si5338 datasheet.
The Si5338 design consists primarily of a single wideband PLL with a bandwidth typically 1.6 MHz, followed by 4 “MultiSynth” dividers which can support four independent output clocks. The MultiSynth dividers are Silicon Labs’ proprietary low jitter fractional dividers that incorporate phase error correction. This whitepaper discusses this approach. Please note that there are other lower jitter clock generators employing similar architectures, with more clock I/O, such as the Si5332. A second injection resistant architectural approach is to embed the potentially susceptible VCO tank circuit in a wideband PLL. (Recall that we want BW > ILBW.) An example jitter attenuator device that improves injection rejection in this way is the Si5380 which uses a nested dual loop architecture as shown in the diagram below. This illustration is taken from the “Optimizing Clock Synthesis in Small Cells and Heterogeneous Networks” whitepaper. In this topology, the LC tank circuit VCO is integrated in a wideband (fast) inner loop which itself acts as the DCO for a narrowband (slow) outer loop. Please note that the Si5380 has been superseded by the more flexible, higher performance Si5386.
References The same references that applied to the previous Timing 201 post apply here. They are listed below, for convenience. Some material covered here was presented at the Austin Conference on Integrated Systems and Circuits (ACISC) in 2009. If you are interested, email me to request a copy of the paper “Practical Issues Measuring and Minimizing Injection Pulling in Board-level Oscillator and PLL Applications” and accompanying slides. As mentioned previously, the best practical overall book treatment of injection lock that I am familiar with is in Wolaver’s text:
This is a slim volume for a PLL book but it punches well above its weight in terms of information. Here are several foundational papers worth reading on the topic of injection.
If you have favorite references you would like to share, please pass them along to me. Conclusion To recap, there are a number of ways that IC, board, and system designers can reduce the risk of injection pulling or injection lock.
Looking ahead, it turns out it is often not practical to straightforwardly calculate the ratio of PINJ/PT and therefore KINJ or ILBW. Next time I will review how one may measure ILBW in the lab. I hope you have enjoyed this Timing 201 article. As always, if you have topic suggestions, or there are questions appropriate for this blog you would like answered, please send them to kevin.smith@silabs.com with the words “Timing 201” in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on. Cheers,
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Feb 07 2020, 8:47 PM |
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kgsmith
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Posted
Timing 201 #3: The Case of the Parasitic PLL - Part 1 on Blog
Introduction Anyone who has had training or experience in high frequency electronics is familiar with the concepts of parasitic capacitance and inductance. These are the unintended “hidden schematic” components that you get when assembling physically realizable circuits. Modeling these elements explicitly may be necessary depending on the application and desired accuracy. It turns out that an independent oscillator can couple energy in to a Phase-Locked Loop’s (PLL’s) VCO so as to influence or even take over the PLL’s output frequency and phase. This is the case of the parasitic PLL. It is a special case of injection as described below. In this post, I will review the basic theory and modeling for this phenomenon. My interest is not in walking through the derivations but rather noting the highlights of the results. This basic bench-level knowledge of injection is useful when designing or applying oscillators and PLLs. Cited references are listed at the end for further study. In the next post I will discuss how to measure injection sensitivity and provide for its mitigation. Motivation Injection locking can actually be useful in certain specific applications such as injection-locked frequency dividers. See Razavi (2004) for example. However, there are several reasons why unintentional injection in PLL frequency synthesis is undesirable:
Unless otherwise noted, this post assumes that the applications of interest involve PLLs which rely on LC resonant tank oscillators. Such circuits are in common use and subject to power supply coupling and external interference. Their Q or quality factor is high enough to yield reasonably good phase noise performance but low enough that injection can be an issue. The emphasis will be on a board level perspective though the same general principles may be applied at lower integration levels. Oscillator Injection Injection pulling or locking refers to when one independent oscillator disturbs or locks the frequency and phase of another independent near-synchronous oscillator. Using crosstalk terminology, the victim oscillator’s frequency is pulled by the aggressor or interferer’s frequency. In the extreme, one oscillator is pulled all the way to lock at another oscillator’s frequency. It is well known that oscillators in close proximity tend to lock to each other. The figure below gives the basic idea. Mechanical injection locking was first observed in pendulum clocks by Dutch scientist Christiaan Huygens in the 17th century. For a modern revisit of this work, see this online paper from Georgia Tech: http://schatzlab.gatech.edu/Library/Bennett2002.pdf.
This is commonly demonstrated in educational settings using metronomes on shared rolling or fixed platforms. See for example http://salt.uaa.alaska.edu/physics_public/metro.html. I have done this myself and it’s a neat demonstration. Analogous behavior can happen in electronics when working with tuned oscillator circuits. Two classic papers on this subject are Adler (1946) and Kurokawa (1973). Independent Oscillators In this context, the term independent oscillator can refer to either asynchronous clocks that are very close (or harmonically close) in frequency or to synchronous clocks that are out of phase. Further, the notion of independence can be extended to synchronous clocks with different phase noise characteristics. The most important example of the latter case is a PLL’s input and output clock domains. Consider a noisy input clock provided to a narrow bandwidth “clean-up” PLL that yields the same frequency output clock. The jitter attenuated output is synchronous to the input clock but independent from a phase noise point of view. Basic Injection Theory My favorite practical treatment on this topic is in Wolaver (1991) and I lean heavily on his work in what follows. Consider the following figures adapted from his book. I use “INJ” subscripts for injection quantities and “T” subscripts for tank quantities for clarity.
In these figures, the following terms apply:
For sustained oscillation the tank circuit must yield a compensating phase shift -Phi1 from VT to V’T and Phi1 = Phi2. The phase of the transfer function VT/ V’T is plotted in the bottom figure. The bottom line is that an injected voltage will result in a phase shift in the oscillator loop. Oscillator Injection Lock Range By assuming that VINJ << VT, Wolaver derived an injection constant or gain where injection acts like a 1st order PLL. Below is a version of Wolaver’s derivation for KINJ with one term re-cast as the square root of a power ratio.
In this figure, the following terms apply:
The derivation suggests several important take-aways, all called out in the figure.
The model below is adapted from Wolaver’s simplest small signal model for a PLL with injection. This version breaks out the injection constant contributions where the angle α represents the phase difference between the injected signal and the input signal.
There are two important features to note in this model.
This last item is most important. Wolaver suggests K > 4 * KINJ. All else being equal, relatively NB (narrow bandwidth) PLLs are more susceptible. Looking ahead to Part 2, the relationship between the nominal (uninjected) and injected PLL BWs will prove useful both in terms of troubleshooting and mitigation. You may recall a previous blog post Timing 101: The Case of the PLL’s VCO High Pass Transfer Function. It pointed out that a relatively wide bandwidth PLL can be used to attenuate VCO intrinsic phase noise. Likewise, a wide bandwidth PLL is also useful to suppress external influences on the VCO such as injection pulling or locking. References Some of the material covered here was presented at the Austin Conference on Integrated Systems and Circuits (ACISC) in 2009. If you are interested, you can email me to request a copy of the paper “Practical Issues Measuring and Minimizing Injection Pulling in Board-level Oscillator and PLL Applications” and accompanying slides. As mentioned previously, the best practical overall book treatment I am familiar with is in Wolaver’s text:
This is a slim volume for a PLL book but it punches well above its weight in terms of information. Here are several foundational papers worth reading on the topic of injection.
If you have favorite references you would like to share, please pass them along to me. Conclusion I hope you have enjoyed this Timing 201 article. Next time, I will follow-up on measuring and minimizing injection sensitivity. As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on. Cheers,
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Feb 07 2020, 8:36 PM |
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kgsmith
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Posted
Timing 201 #4: The Case of the Parasitic PLL - Part 2 on Blog
Introduction In the last Timing 201 post, I discussed the parasitic Phase-Locked Loop (PLL) in which an independent oscillator can couple energy in to a PLL’s VCO so as to influence or even take over the PLL’s output frequency and phase. I then reviewed some basic injection theory, including the concept of injection lock range. Given the amount of material I would like to cover, I am going to follow-up that post with two more articles. This installment, Part 2, will discuss how to minimize injection sensitivity generally. Part 3, to come later, will cover the topic of measuring injection sensitivity. A Brief Review Per the last article, injection pulling or locking refers to when one independent oscillator disturbs or locks the frequency and phase of another independent near-synchronous oscillator. We then reviewed injection theory after Wolaver (1991) culminating in this equation with the important take-aways noted.
ILBW (Injection Lock Bandwidth) Wolaver treated the injection constant or gain KINJ as the injection lock range. It is useful to regard this lock range as the Injection Lock Bandwidth (ILBW) to contrast it with the PLL’s loop bandwidth (BW). From here on, I will use this nomenclature. The bottom line is that, in order to minimize the risk of injection locking, we want BW > ILBW. Ideally, BW would be significantly greater than the PLL’s ILBW. The factors in the formula suggest where we might run in to trouble. For example, LC tank oscillators, especially when integrated, have much lower Q compared to crystal oscillators. Further, the trend is for higher and higher frequency clocks. The resonant tank frequency itself is usually dictated by something on the order of 2 times the maximum 50% duty cycle output clock frequency we would like to support. So we should be on guard for this issue when considering narrow band (NB) and high frequency low-Q VCO tank circuit PLLs. So why don’t we routinely run in to injection problems today? Well you still can, if you are rolling your own NB discrete synchronous PLLs and especially if you co-locate them. This article series is in part an attempt to warn you of some possible concerns. Board and IC designers have learned over the years to adopt injection resistant practices and PLL topologies. First, let’s begin by considering some typical injection mechanisms. Injection Mechanisms There are several common injection mechanisms in which aggressor oscillator noise may couple in to a tank oscillator circuit. The first two listed are suggested by the figure below:
We can mitigate, or reduce the impact, of injection by directly addressing these injection mechanisms and/or by using more injection resistant system-level approaches. Injection Mitigation via Good EMC Design Injection can be regarded as a special topic within the field of EMC (Electromagnetic Compatibility). We can minimize injection noise power applied at the tank for each of these mechanisms using good practices for designers cognizant of general Electromagnetic Interference (EMI) issues.
All of the above methods attack the problem by reducing the strength of the aggressor noise PINJ. However, in addition to these direct approaches, there are some other more systemic ways of minimizing injection problems. Injection Mitigation via Thoughtful Frequency Planning You may recall that I mentioned the general problem of injection pulling and locking arises when working with signals and oscillators that are synchronous or nearly so. What do I mean by nearly-synchronous? A SONET application board with lots of clock I/O all running at or near SONET frequencies within a few ppm of each other is a classic example. One approach, if you have multiple PLLs or clock devices co-located on the same printed circuit board, is to configure them so that the VCO frequencies are asynchronous from each other. For example, consider an application where you have two adjacent Si570 I2C-Programmable XOs on a PCB. You can minimize the risk of injection crosstalk (XTALK) by configuring the devices so that their internal DCOs or Digitally Controlled Oscillators are well off frequency from each other. Consider the Si570 Detailed Block Diagram below taken from this datasheet. In the diagram, HS_DIV refers to the DCO High Speed Divider with possible values [4-7, 9, 11]. N1 is the CLKOUT Output Divider with allowed values [1] and [2, 4, 6, …, 27]. Finally, the datasheet constrains the DCO frequency to 4.850 GHz £ fosc £ 5.67 GHz. Given these constraints, there can often be multiple frequency plan solutions that output the same clock frequency.
For example, the DCOs can be made significantly asynchronous even when the output clocks are identical in frequency. Here are two valid Si570 configurations that both yield f1 = 155.52 MHz outputs.
In this instance, each DCO frequency is asynchronous, greatly minimizing the risk of injection XTALK. Injection Mitigation via Beneficial Clock Architectures One architectural approach is to simply minimize the number of PLLs, and therefore VCOs, with associated tank circuits, that might be susceptible to injection XTALK. An example clock generator that minimizes the number of PLLs is the Si5338 I2C-Programmable Any-Frequency, Any-Output Quad Clock Generator. The functional block diagram below is taken from the Si5338 datasheet.
The Si5338 design consists primarily of a single wideband PLL with a bandwidth typically 1.6 MHz, followed by 4 “MultiSynth” dividers which can support four independent output clocks. The MultiSynth dividers are Silicon Labs’ proprietary low jitter fractional dividers that incorporate phase error correction. This whitepaper discusses this approach. Please note that there are other lower jitter clock generators employing similar architectures, with more clock I/O, such as the Si5332. A second injection resistant architectural approach is to embed the potentially susceptible VCO tank circuit in a wideband PLL. (Recall that we want BW > ILBW.) An example jitter attenuator device that improves injection rejection in this way is the Si5380 which uses a nested dual loop architecture as shown in the diagram below. This illustration is taken from the “Optimizing Clock Synthesis in Small Cells and Heterogeneous Networks” whitepaper. In this topology, the LC tank circuit VCO is integrated in a wideband (fast) inner loop which itself acts as the DCO for a narrowband (slow) outer loop. Please note that the Si5380 has been superseded by the more flexible, higher performance Si5386.
References The same references that applied to the previous Timing 201 post apply here. They are listed below, for convenience. Some material covered here was presented at the Austin Conference on Integrated Systems and Circuits (ACISC) in 2009. If you are interested, email me to request a copy of the paper “Practical Issues Measuring and Minimizing Injection Pulling in Board-level Oscillator and PLL Applications” and accompanying slides. As mentioned previously, the best practical overall book treatment of injection lock that I am familiar with is in Wolaver’s text:
This is a slim volume for a PLL book but it punches well above its weight in terms of information. Here are several foundational papers worth reading on the topic of injection.
If you have favorite references you would like to share, please pass them along to me. Conclusion To recap, there are a number of ways that IC, board, and system designers can reduce the risk of injection pulling or injection lock.
Looking ahead, it turns out it is often not practical to straightforwardly calculate the ratio of PINJ/PT and therefore KINJ or ILBW. Next time I will review how one may measure ILBW in the lab. I hope you have enjoyed this Timing 201 article. As always, if you have topic suggestions, or there are questions appropriate for this blog you would like answered, please send them to kevin.smith@silabs.com with the words “Timing 201” in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on. Cheers,
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Feb 07 2020, 12:16 AM |
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Posted Can the Si4133 AUXOUT be treated as an SPI MISO line? on Knowledge Base Show more |
Oct 07 2019, 11:52 PM |
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Posted Can a single-ended external reference clock be connected to an Si534x/7x/8x/9x device's XB pin? on Knowledge Base Show more |
Oct 07 2019, 11:30 PM |
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Updated
Timing 201 #2: The Case of the Phase Noise That Wasn’t - Part 2 on Blog
Introduction Hello and welcome to the latest article for the blog series, Timing 201. This is a sequel to the article Timing 201 #1: The Case of the Phase Noise That Wasn’t – Part 1. In this post, I follow-up on Part 1 and suggest that both a limiting amplifier and balun are useful accessories to minimize AM and make good phase noise measurements. I include some example data and close with a few rules of thumb. A Quick Review from Part 1 You will recall the basic idea we last explored was that AM (Amplitude Modulation) noise can impact phase noise measurements. (AM noise is the apparent “phase noise that isn’t”.) A spectrum analyzer cannot distinguish between AM and PM (Phase Modulation) or phase noise. Purpose-built phase noise measurement instrumentation can suppress but not eliminate AM to PM conversion. The use of a limiting amplifier can further reduce the impact of AM noise on phase noise measurement. This can be a valuable troubleshooting tool when investigating system-level clock noise and spurs. Example Limiting Amplifier AM Rejection First, a few words about the particular limiting amplifier used for data collection in this article. The ideal limiting amplifier or LA would be high gain, low noise, wideband, and modestly priced. That combination is hard to find. The sample LA used here is the Hittite (now Analog Devices) HMC750 which has a 3 dB bandwidth of 11 GHz. An evaluation board is available from distributors though it’s relatively expensive. There are other LAs available from other vendors, and if you buy units in quantity and/or roll your own PCB, you can certainly lower your costs. Two suggestions if you do use the Hittite evaluation board:
As a reminder, the time domain operation of the LA is illustrated as follows. Below left is a scope capture for a 100 MHz single-ended sinusoidal clock. The AM depth was 5% and the scope is set to infinite persistence. Below right is the same single-ended clock through the example limiting amplifier.
While the time domain operation is suggestive, AM rejection is better measured in the frequency domain. In the following measurements, a Keysight E5052B was used both as the measurement instrument and as a stand-in clock receiver. I employed a Keysight 33600A Waveform Generator, operating single-endedly, to apply AM at several frequencies and measured both the AM and phase noise spur amplitude. The carrier was 100 MHz and the AM depth was set to 1%. Getting a consistent AM spur above the noise floor was what I was looking for.
I then inserted the cited LA and repeated the same measurements.
Note the new noise columns that had to be added. The LA effectively eliminated the AM spur completely, reducing it to the noise floor. There is still a corresponding phase noise spur, reduced also. (Subsequent testing indicated this was incidental phase modulation from the source.) Here is a sample plot for the 100 kHz case with no intervening limiting amplifier. The phase noise window is displayed at the top and the AM noise window is displayed at the bottom. Marker 1 in each window is set at 100 kHz.
And here is a corresponding sample plot for the 100 kHz case when using the limiting amplifier. As I mentioned previously, the AM spur is eliminated which I was looking for. The corresponding phase noise spur dropped another 12 dB. For some reason, at least for this sample, the AM noise floor above 10 kHz is not flat as would be ideal.
In general, we should use a limiting amplifier if AM noise or spurs are significant with respect to phase noise. In a measurement system that can measure both, we typically want AM noise or spurs to be at least 10 dB below phase noise or spurs at the same offset frequencies. (We weren’t quite getting that in the first table above.) Ideally, the same would be true for the clock receiver accounting for its AM rejection. For example, if both the input clock’s AM noise floor and phase noise floor were the same at a particular offset frequency, then we would want the clock receiver to reject or attenuate AM noise further by 10 dB. This performance is not always specified and may need to be measured. It is also often a function of the input clock slew rate or rise/fall time. Differential Signaling A limiting amplifier is useful for removing AM from both single-ended and differential clocks. However, differential clocks are themselves an important approach to combating AM noise. One of the most important reasons for differential signaling on balanced lines is common mode (CM) noise rejection. Since most AM noise on differential signals is CM (e.g. due to power supplies) then differential receivers will tend to reject AM. This can be illustrated pictorially in the figures below. First, consider amplitude noise impressed upon a single-ended clock.
Now, consider the same amplitude noise impressed upon a differential clock.
There are several aspects to the diagram worth noting:
All of these will help to prevent CM AM noise from impacting the measurement. Unfortunately, most spectrum and phase noise analysis instruments have single-ended inputs and don’t directly support differential measurements. If we replace the receiver in the diagram with an instrument, what is the best approach? A ready measurement would be to route one differential clock polarity, e.g. CLKP, to the instrument and terminate the unmeasured polarity output, e.g. CLKN, in to 50 Ω. Generally you will want to AC-couple these so as to present roughly the same impedance. The necessity for balanced termination is discussed in Timing 101 #10: The Case of the Half-terminated Differential Output Clock. This is a valid measurement but is overly conservative as it neglects the advantage that would actually be experienced in a differential clock system. What we need is a device that will convert the differential signal to a single-ended signal. Such a device is known as a balun (taken from balanced to unbalanced). This could be in the form of an amplifier (sometimes called an active balun) or more typically a passive component. As an example of the latter, a classic transformer balun or voltage balun has a center-tapped winding on one side for converting 100 Ω differential to single-ended 50 Ω. The example balun used in these tests is the Tektronix (formerly Picosecond Pulse Labs) PSPL5310R. This is a phase matched balun which can operate from 4 MHz to 6.5 GHz. Unfortunately, for some reason, these are no longer available from Tektronix. Other vendors which sell baluns include MACOM, Marki Microwave, and Mini-Circuits. (This is not meant to be an inclusive and exhaustive list. These are just companies I am familiar with.) Look for a balun wideband enough to pass the necessary waveform with sufficient risetime and with good phase and amplitude balance. The old PSPL balun had anywhere from ± 0.5 to ± 2 degrees differential phase balance and ± 0.1 to +0.3/0.2 dB differential amplitude balance depending on the frequency range. Example DUT with AM Noise I have selected for a practical example one of my favorite “desert island” parts, the venerable Si570 which is an older generation programmable oscillator. It was the first 5 mm x 7 mm I2C programmable oscillator that could cover 10 MHz to 1.4 GHz. Radio amateurs may recognize this device as used in some “Softrock” SDR (Software Defined Radio) applications. Not only can it support such a wide frequency range but it can also be ordered with “real” LVPECL drivers. By this I mean it can drive DC-coupled LVPECL loads defined as 50 Ω terminated in to VDD – 2V. (By contrast, clock devices typically provide LVPECL compatible modes where they can supply the right swing when AC-coupled.) There is some CM (Common Mode) AM noise using this mode. However, this is mitigated when used differentially as intended. Below we will tabulate several measurement scenarios with and without a balun and LA. The DUT is an evaluation board with P/N 570AAA000121DG installed operating AC-coupled. This is a differential programmable XO with a 100 MHz starting frequency, output format 3.3V LVPECL. Here are the phase jitter results for various configurations.
The biggest bang for the buck so to speak was using a balun. That got us to the 300fs range or less which is what we expect this device to yield. (The closest Si570 datasheet spec is 360 fs typical for Fout from 125 to 500 MHz.) Here are a few plots to go with this table. First, the single-ended configuration with the highest phase jitter, over 600 fs. Note the several spurs above 1 MHz in both the AM and phase noise measurement windows.
Next is the balun only configuration which eliminates some spurs and drops the phase jitter roughly in half, i.e. below 300 fs.
Finally, here is the phase noise plot combining the DUT driving the LA differentially which in turn drives the balun connected to the E5052B. This plot eliminates all the spurs above 1 MHz and still keeps the phase noise floor mostly below -150 dBc/Hz beyond this offset frequency.
Virtual Limiting Amplifier Ignoring spurs, it is possible in principle to estimate the DUT’s post-LA phase noise performance by mathematically applying a “virtual limiting amplifier”, if you know what the LA AM noise floor will be and what the AM to PM conversion is for your instrument. However, that is a topic for another time. In practice, as one peels the onion to achieve lower and lower phase noise measurements, spurs play an increasingly larger role. This can be problematic for estimation purposes since even if the location of spurs can be predicted, often their amplitudes cannot. A Few Rules of Thumb Based on this and the previous Timing 201 post, here are a few suggested rules of thumb when making phase noise measurements on sources that may have AM noise:
Having a good limiting amplifier and a good balun on your bench can help you make more accurate phase noise and jitter measurements, and help distinguish the type of noise contributors you are dealing with. If you are working with differential clocks, you really should use a balun even if AM noise is not that significant. Conclusion I hope you have enjoyed this Timing 201 article. If you have a favorite balun or limiting amplifier you would like to share with others, please let me know. As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words “Timing 201” in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on. Cheers, Kevin |
Sep 26 2019, 8:00 PM |
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