Profile Data
| Member | Action | Date |
|---|---|---|
Tracy Boyd
|
Updated
Timing 201 #9: The Case of the Really Slow Jitter – Part 1 on Blog
Introduction You have probably read or heard that phase noise is the frequency domain equivalent of jitter in the time domain. That is essentially correct except for what would appear to be a somewhat arbitrary dividing line. Phase noise below 10 Hz offset frequency is generally considered wander as opposed to jitter. Consider the screen capture below where I have measured phase noise down to 1 Hz minimum offset and explicitly noted the 10 Hz dividing line. Wander is on the left hand side and jitter is on the right hand side. The phase noise plot trends as one might expect right through the 10 Hz line. So what’s different about wander as opposed to jitter and why do we care? From the perspective of someone who takes a lot of phase noise plots, I consider this the case of the really slow jitter. It’s both slow in terms of phase modulation and in how long it takes to measure.
The topic of wander covers a lot of material. Even introducing the highlights will take more than one blog article. In this first post, I will discuss the differences between wander and jitter, the motivation for understanding wander, and go in to some detail regarding a primary wander metric: MTIE or Maximum Time Interval Error. Next in this mini-series, I will discuss TDEV or Time Deviation. Finally, I plan to wrap up with some example lab data. Some Formal Definitions The 10 Hz dividing line, in common use today, has been used in synchronous optical networking (SONET) and synchronous digital hierarchy (SDH) standards for years. For example, ITU-T G.810 (08/96) Definitions and terminology for synchronization networks [1] defines jitter and wander as follows. 4.1.12 (timing) jitter: The short-term variations of the significant instants of a timing signal from their ideal positions in time (where short-term implies that these variations are of frequency greater than or equal to 10 Hz). 4.1.15 wander: The long-term variations of the significant instants of a digital signal from their ideal position in time (where long-term implies that these variations are of frequency less than 10 Hz). Similarly, the SONET standard Telcordia GR-253-CORE [2] states in a footnote “Short-term variations” implies phase oscillations of frequency greater than or equal to some demarcation frequency. Currently, 10 Hz is the demarcation between jitter and wander in the DS1 to DS3 North American Hierarchy. Wander and jitter are clearly very similar since they are both “variations of the significant instants of a timing signal from their ideal positions in time”. They are also both ways of looking at phase fluctuations or angle modulation (PM or FM). Their only difference would appear to be scale. However, that can be a significant practical difference. Consider by analogy the electromagnetic radiation spectrum, which is divided into several different bands such as infrared, visible light, radio waves, microwaves, and so forth. In some sense, these are all “light”. However, the different types of EM radiation are generated and detected differently and interact with materials differently. So it has always made historical and practical sense to divide the spectrum into bands. This is roughly analogous to the wander versus jitter case in that these categories of phase fluctuations differ technologically. Why 10Hz? So, how did this 10 Hz demarcation frequency come about? Generally speaking, wander represented timing fluctuations that could not be attenuated by typical PLLs of the day. PLLs in the network elements would just track wander, and so it could accumulate. Networks have to use other means such as buffers or pointer adjustments to accommodate or mitigate wander. Think of the phase noise offset region, 10 Hz and above, as “PLL Land”. Things have changed since these standards. Back in the day it was uncommon or impractical to measure phase noise below 10 Hz offset. Now phase noise test equipment can go down to 1 Hz or below. Likewise with digital and FW/SW PLLs it is possible to have very narrowband PLLs which can provide some “wander attenuation”. Nonetheless, 10 Hz offset remains a useful dividing line and lives on in the standards. Wander Mechanisms Clock jitter is due to the relatively high frequency inherent or intrinsic jitter of an oscillator or other reference ultimately caused by flicker noise, shot noise, and thermal noise. Post processing by succeeding devices such as clock buffers, clock generators, and jitter attenuators can contribute to or attenuate this random noise. Systemic or deterministic jitter components also can occur due to crosstalk, EMI, power supply noise, reflections etc. Wander, on the other hand, is caused by slower processes. These include lower frequency offset oscillator and clock device noise components, plus the following.
For a good discussion of some of these wander mechanisms and their impact on a network, see [3]. Since wander mechanisms are different, at least in scale, and networks tend to pass or accumulate wander, industry has focused on understanding and limiting wander through specifications and standards. Wander Terminology and Metrics You may recall the use of the terms jitter generation, jitter transfer, and jitter tolerance. These measurements can be summarized as follows.
These definitions generally apply to phase noise measurements made with frequency domain equipment such as phase noise analyzers or spectrum analyzers. They are useful when cascading network elements. By contrast, wander is typically measured with time domain equipment. Counterpart definitions apply as listed below.
Wander has its own peculiar metrics too. In particular, standards bodies such as the ITU rely on masks that provide limits to wander generation, tolerance, and transfer based on one or both of the following two wander parameters. See for example ITU-T 8262 [4].
Very briefly, MTIE looks at peak-peak clock noise over intervals of time as we will discuss below. TDEV is a sort of standard deviation of the clock noise after some filtering. We will discuss TDEV next time. Before going into detail about MTIE, let’s discuss the foundational measurements Time Error and TIE (Time Interval Error). These are both defined in the previously cited ITU-T G.810. Time Error (TE) The Time Error function x(t) is defined as follows for a measured clock generating time T(t) versus a reference clock generating time Tref(t). The frequency standard Tref(t) can be regarded as ideal, i.e., Tref(t) = t.
Time Interval Error (TIE) Similarly, the Time Interval Error function is then defined as follows, where the lower case Greek letter "tau" is the time interval or observation interval.
Maximum Time Interval Error (MTIE)
The sampling period represents the minimum measurement interval or observation interval. There are many terms used in the industry that are synonymous and should be recognizable in context: averaging time, sampling interval, sampling time, etc. This could mean every nominal period if you are using an oscilloscope to capture TIE data. However, most practical measurements over long periods of time are only sampling clocks. This would correspond to a frequency counter’s “gate time”, for example, if post-processing frequency data to obtain phase data. An MTIE Example It’s better to show you the general idea at this point. Below, I have modified an illustration after ITU-T G.810 Figure II.1 and indicated a tau=1*tau0 observation interval or window as it is moved across the data. (The data are for example only and do not come from the standard. I have also started at 0 as is customary to show changes in Time Error or phase since the start of the measurement.) The initial xppk peak-peak value at the location shown is about 1.1 ns – 0 ns = 1.1 ns.
Now slide the tau=1*tau0 observation interval right and the next xppk peak-peak value is 1.4 ns – 1.1 ns = 0.3 ns.
If we continue in this vein to the end of the data, we will find the worst case to be between 17*tau0 and 18*tau0 and the value is 7.0 ns – 4.0 ns = 3.0 ns. Therefore, the MTIE for tau=1*tau0 is 3.0 ns. I have calculated the MTIE plot for this dataset in the attached Excel spreadsheet Example_MTIE_Calcs.xlsx. Note that the first value in the plot is 3 ns as just mentioned. This is a relatively simple example for illustration only. MTIE data typically spans many decades and are plotted against masks on logarithmic scales.
However, even this simple example suggests a couple of items to note about MTIE plots:
Why is MTIE Useful? MTIE is a relatively computation intensive measurement. So what good are these type of plots? There are at least two good reasons besides standards compliance:
Conclusion In this post, I have discussed the differences between wander and jitter, the motivation for understanding wander, and delved in to MTIE, a wander metric important to standards compliance and useful in sizing buffers. I hope you have enjoyed this Timing 201 article. In the Part 2 follow-up post, I will discuss another important wander metric: TDEV or Time Deviation. As always, if you have topic suggestions or questions appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on. Cheers, References [1] ITU-T G.810 Definitions and terminology for synchronization networks [2] Telcordia GR-253-CORE, Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria [3] Understanding Jitter and Wander Measurements and Standards, 2003 [4] ITU-T G.8262 Timing characteristics of a synchronous equipment slave clock [5] K. Shenoi, Clocks, Oscillators, and PLLs, An introduction to synchronization and timing in telecommunications, WSTS – 2013, San Jose, April 16-18, 2013 [6] L. Cossart, Timing Measurement Fundamentals, ITSF November 2006.
|
60 days ago |
|
Tracy Boyd
|
Updated
Timing 201 #9: The Case of the Really Slow Jitter – Part 1 on Blog
Introduction You have probably read or heard that phase noise is the frequency domain equivalent of jitter in the time domain. That is essentially correct except for what would appear to be a somewhat arbitrary dividing line. Phase noise below 10 Hz offset frequency is generally considered wander as opposed to jitter. Consider the screen capture below where I have measured phase noise down to 1 Hz minimum offset and explicitly noted the 10 Hz dividing line. Wander is on the left hand side and jitter is on the right hand side. The phase noise plot trends as one might expect right through the 10 Hz line. So what’s different about wander as opposed to jitter and why do we care? From the perspective of someone who takes a lot of phase noise plots, I consider this the case of the really slow jitter. It’s both slow in terms of phase modulation and in how long it takes to measure.
The topic of wander covers a lot of material. Even introducing the highlights will take more than one blog article. In this first post, I will discuss the differences between wander and jitter, the motivation for understanding wander, and go in to some detail regarding a primary wander metric: MTIE or Maximum Time Interval Error. Next in this mini-series, I will discuss TDEV or Time Deviation. Finally, I plan to wrap up with some example lab data. Some Formal Definitions The 10 Hz dividing line, in common use today, has been used in synchronous optical networking (SONET) and synchronous digital hierarchy (SDH) standards for years. For example, ITU-T G.810 (08/96) Definitions and terminology for synchronization networks [1] defines jitter and wander as follows. 4.1.12 (timing) jitter: The short-term variations of the significant instants of a timing signal from their ideal positions in time (where short-term implies that these variations are of frequency greater than or equal to 10 Hz). 4.1.15 wander: The long-term variations of the significant instants of a digital signal from their ideal position in time (where long-term implies that these variations are of frequency less than 10 Hz). Similarly, the SONET standard Telcordia GR-253-CORE [2] states in a footnote “Short-term variations” implies phase oscillations of frequency greater than or equal to some demarcation frequency. Currently, 10 Hz is the demarcation between jitter and wander in the DS1 to DS3 North American Hierarchy. Wander and jitter are clearly very similar since they are both “variations of the significant instants of a timing signal from their ideal positions in time”. They are also both ways of looking at phase fluctuations or angle modulation (PM or FM). Their only difference would appear to be scale. However, that can be a significant practical difference. Consider by analogy the electromagnetic radiation spectrum, which is divided into several different bands such as infrared, visible light, radio waves, microwaves, and so forth. In some sense, these are all “light”. However, the different types of EM radiation are generated and detected differently and interact with materials differently. So it has always made historical and practical sense to divide the spectrum into bands. This is roughly analogous to the wander versus jitter case in that these categories of phase fluctuations differ technologically. Why 10Hz? So, how did this 10 Hz demarcation frequency come about? Generally speaking, wander represented timing fluctuations that could not be attenuated by typical PLLs of the day. PLLs in the network elements would just track wander, and so it could accumulate. Networks have to use other means such as buffers or pointer adjustments to accommodate or mitigate wander. Think of the phase noise offset region, 10 Hz and above, as “PLL Land”. Things have changed since these standards. Back in the day it was uncommon or impractical to measure phase noise below 10 Hz offset. Now phase noise test equipment can go down to 1 Hz or below. Likewise with digital and FW/SW PLLs it is possible to have very narrowband PLLs which can provide some “wander attenuation”. Nonetheless, 10 Hz offset remains a useful dividing line and lives on in the standards. Wander Mechanisms Clock jitter is due to the relatively high frequency inherent or intrinsic jitter of an oscillator or other reference ultimately caused by flicker noise, shot noise, and thermal noise. Post processing by succeeding devices such as clock buffers, clock generators, and jitter attenuators can contribute to or attenuate this random noise. Systemic or deterministic jitter components also can occur due to crosstalk, EMI, power supply noise, reflections etc. Wander, on the other hand, is caused by slower processes. These include lower frequency offset oscillator and clock device noise components, plus the following.
For a good discussion of some of these wander mechanisms and their impact on a network, see [3]. Since wander mechanisms are different, at least in scale, and networks tend to pass or accumulate wander, industry has focused on understanding and limiting wander through specifications and standards. Wander Terminology and Metrics You may recall the use of the terms jitter generation, jitter transfer, and jitter tolerance. These measurements can be summarized as follows.
These definitions generally apply to phase noise measurements made with frequency domain equipment such as phase noise analyzers or spectrum analyzers. They are useful when cascading network elements. By contrast, wander is typically measured with time domain equipment. Counterpart definitions apply as listed below.
Wander has its own peculiar metrics too. In particular, standards bodies such as the ITU rely on masks that provide limits to wander generation, tolerance, and transfer based on one or both of the following two wander parameters. See for example ITU-T 8262 [4].
Very briefly, MTIE looks at peak-peak clock noise over intervals of time as we will discuss below. TDEV is a sort of standard deviation of the clock noise after some filtering. We will discuss TDEV next time. Before going into detail about MTIE, let’s discuss the foundational measurements Time Error and TIE (Time Interval Error). These are both defined in the previously cited ITU-T G.810. Time Error (TE) The Time Error function x(t) is defined as follows for a measured clock generating time T(t) versus a reference clock generating time Tref(t). The frequency standard Tref(t) can be regarded as ideal, i.e., Tref(t) = t.
Time Interval Error (TIE) Similarly, the Time Interval Error function is then defined as follows, where the lower case Greek letter "tau" is the time interval or observation interval.
Maximum Time Interval Error (MTIE)
The sampling period represents the minimum measurement interval or observation interval. There are many terms used in the industry that are synonymous and should be recognizable in context: averaging time, sampling interval, sampling time, etc. This could mean every nominal period if you are using an oscilloscope to capture TIE data. However, most practical measurements over long periods of time are only sampling clocks. This would correspond to a frequency counter’s “gate time”, for example, if post-processing frequency data to obtain phase data. An MTIE Example It’s better to show you the general idea at this point. Below, I have modified an illustration after ITU-T G.810 Figure II.1 and indicated a tau=1*tau0 observation interval or window as it is moved across the data. (The data are for example only and do not come from the standard. I have also started at 0 as is customary to show changes in Time Error or phase since the start of the measurement.) The initial xppk peak-peak value at the location shown is about 1.1 ns – 0 ns = 1.1 ns.
Now slide the tau=1*tau0 observation interval right and the next xppk peak-peak value is 1.4 ns – 1.1 ns = 0.3 ns.
If we continue in this vein to the end of the data, we will find the worst case to be between 17*tau0 and 18*tau0 and the value is 7.0 ns – 4.0 ns = 3.0 ns. Therefore, the MTIE for tau=1*tau0 is 3.0 ns. I have calculated the MTIE plot for this dataset in the attached Excel spreadsheet Example_MTIE_Calcs.xlsx. Note that the first value in the plot is 3 ns as just mentioned. This is a relatively simple example for illustration only. MTIE data typically spans many decades and are plotted against masks on logarithmic scales.
However, even this simple example suggests a couple of items to note about MTIE plots:
Why is MTIE Useful? MTIE is a relatively computation intensive measurement. So what good are these type of plots? There are at least two good reasons besides standards compliance:
Conclusion In this post, I have discussed the differences between wander and jitter, the motivation for understanding wander, and delved in to MTIE, a wander metric important to standards compliance and useful in sizing buffers. I hope you have enjoyed this Timing 201 article. In the Part 2 follow-up post, I will discuss another important wander metric: TDEV or Time Deviation. As always, if you have topic suggestions or questions appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on. Cheers, References [1] ITU-T G.810 Definitions and terminology for synchronization networks [2] Telcordia GR-253-CORE, Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria [3] Understanding Jitter and Wander Measurements and Standards, 2003 [4] ITU-T G.8262 Timing characteristics of a synchronous equipment slave clock [5] K. Shenoi, Clocks, Oscillators, and PLLs, An introduction to synchronization and timing in telecommunications, WSTS – 2013, San Jose, April 16-18, 2013 [6] L. Cossart, Timing Measurement Fundamentals, ITSF November 2006.
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60 days ago |
|
Tracy Boyd
|
Posted
Factories are Dirty: How to Protect 24 V Digital Inputs & Outputs in Industrial Environments on Blog
Industrial environments demand a lot from control systems. Devices such as programmable logic controllers (PLCs) must operate continuously with various components and as little maintenance and downtime as possible. However, a PLC is only as good as the input /output capabilities of the digital channels connected to the industrial ecosystem. Harsh, noisy environments and various unknown factors can all contribute to design challenges that affect digital channel reliability, resulting in possible circuit damage, downtime, and system failure. In the dual webinar sessions, Protecting 24 V Digital Outputs from the Unknown and Factories are Dirty – Protecting Industrial Digital Inputs, senior product manager Asa Kirby and applications engineers Travis Lenz and Kevin Huang describe the design challenges specific to industrial digital channels and how to mitigate them using Silicon Labs' Si834x and Si838x digital isolator devices. Environmental Challenges 
Industrial ecosystems present a multitude of conditions that can result in damage to digital input and output channels. The most common challenges include:
Input/output-specific challenges include managing overload conditions and driving inductive loads for outputs and device compatibility and assembly/installation protection for inputs. Industrial systems must be able to handle all these varied design challenges while operating in harsh environments.
Silicon Labs’ Digital Isolator Solutions Silicon Labs' digital isolators provide optimal solutions to the unique challenges of industrial environments. Our Si834x isolated smart switches are ideal for driving resistive and inductive loads, including solenoids, relays, and lamps commonly found in industrial control systems. They are fully compliant with IEC61131-2, so they interoperate well with other channels. Each switch can detect an open circuit condition and is protected against over-current, over-voltage from demagnetization (inductive kick or flyback voltage), and over-temperature conditions. An innovative multi-voltage smart clamp can manage an unlimited amount of demagnetization energy (EAS). Si834x switches are available in Parallel or SPI input types and sourcing or sinking output types. With substantial power savings and a compact 9x9 DFN package, these switches reduce board space and design headache! 
Our Si838x isolated multi-channel input isolators are high-density, highly flexible devices that are ideal replacements for traditional optocouplers. They offer eight channels of 24 V digital field interface in a single compact QSOP package with integrated safety rated isolation. With a few external components, this structure provides compliance to IEC 61131-2 switch types 1, 2, or 3. The input interface is built on our ground-breaking CMOS-based LED emulator technology, which means the devices can handle sourcing or sinking configurations without a power supply on the field side. By utilizing our proprietary silicon isolation technology, these devices support up to 2.5 kV RMS withstand voltage, enabling high-speed capability, high noise immunity of 25 kV/µs, reduced variation with temperature and age, and better part-to-part matching. One Si838x isolator can replace eight traditional optocouplers, making them ideal solutions for space-constrained industrial facilities. 
Watch these webinars to learn more about how our digital isolators provide optimal solutions to the unique challenges and harsh conditions of industrial environments: Protecting 24 V Digital Outputs and Factories are Dirty. To learn more about our Si834x and Si838x devices, contact your Silicon Labs sales representative. |
Mar 17 2021, 4:39 PM |
|
Tracy Boyd
|
Updated
Factories are Dirty: How to Protect 24 V Digital Inputs & Outputs in Industrial Environments on Blog
Industrial environments demand a lot from control systems. Devices such as programmable logic controllers (PLCs) must operate continuously with various components and as little maintenance and downtime as possible. However, a PLC is only as good as the input /output capabilities of the digital channels connected to the industrial ecosystem. Harsh, noisy environments and various unknown factors can all contribute to design challenges that affect digital channel reliability, resulting in possible circuit damage, downtime, and system failure. In the dual webinar sessions, Protecting 24 V Digital Outputs from the Unknown and Factories are Dirty – Protecting Industrial Digital Inputs, senior product manager Asa Kirby and applications engineers Travis Lenz and Kevin Huang describe the design challenges specific to industrial digital channels and how to mitigate them using Silicon Labs' Si834x and Si838x digital isolator devices. Environmental Challenges
Industrial ecosystems present a multitude of conditions that can result in damage to digital input and output channels. The most common challenges include:
Input/output-specific challenges include managing overload conditions and driving inductive loads for outputs and device compatibility and assembly/installation protection for inputs. Industrial systems must be able to handle all these varied design challenges while operating in harsh environments. Silicon Labs’ Digital Isolator Solutions Silicon Labs' digital isolators provide optimal solutions to the unique challenges of industrial environments. Our Si834x isolated smart switches are ideal for driving resistive and inductive loads, including solenoids, relays, and lamps commonly found in industrial control systems. They are fully compliant with IEC61131-2, so they interoperate well with other channels. Each switch can detect an open circuit condition and is protected against over-current, over-voltage from demagnetization (inductive kick or flyback voltage), and over-temperature conditions. An innovative multi-voltage smart clamp can manage an unlimited amount of demagnetization energy (EAS). Si834x switches are available in Parallel or SPI input types and sourcing or sinking output types. With substantial power savings and a compact 9x9 DFN package, these switches reduce board space and design headache!
Our Si838x isolated multi-channel input isolators are high-density, highly flexible devices that are ideal replacements for traditional optocouplers. They offer eight channels of 24 V digital field interface in a single compact QSOP package with integrated safety rated isolation. With a few external components, this structure provides compliance to IEC 61131-2 switch types 1, 2, or 3. The input interface is built on our ground-breaking CMOS-based LED emulator technology, which means the devices can handle sourcing or sinking configurations without a power supply on the field side. By utilizing our proprietary silicon isolation technology, these devices support up to 2.5 kV RMS withstand voltage, enabling high-speed capability, high noise immunity of 25 kV/µs, reduced variation with temperature and age, and better part-to-part matching. One Si838x isolator can replace eight traditional optocouplers, making them ideal solutions for space-constrained industrial facilities.
Watch these webinars to learn more about how our digital isolators provide optimal solutions to the unique challenges and harsh conditions of industrial environments: Protecting 24 V Digital Outputs and Factories are Dirty. To learn more about our Si834x and Si838x devices, contact your Silicon Labs sales representative. |
Mar 17 2021, 4:39 PM |
|
Tracy Boyd
|
Updated
Factories are Dirty: How to Protect 24 V Digital Inputs & Outputs in Industrial Environments on Blog
Industrial environments demand a lot from control systems. Devices such as programmable logic controllers (PLCs) must operate continuously with various components and as little maintenance and downtime as possible. However, a PLC is only as good as the input /output capabilities of the digital channels connected to the industrial ecosystem. Harsh, noisy environments and various unknown factors can all contribute to design challenges that affect digital channel reliability, resulting in possible circuit damage, downtime, and system failure. In the dual webinar sessions, Protecting 24 V Digital Outputs from the Unknown and Factories are Dirty – Protecting Industrial Digital Inputs, senior product manager Asa Kirby and applications engineers Travis Lenz and Kevin Huang describe the design challenges specific to industrial digital channels and how to mitigate them using Silicon Labs' Si834x and Si838x digital isolator devices. Environmental Challenges
Industrial ecosystems present a multitude of conditions that can result in damage to digital input and output channels. The most common challenges include:
Input/output-specific challenges include managing overload conditions and driving inductive loads for outputs and device compatibility and assembly/installation protection for inputs. Industrial systems must be able to handle all these varied design challenges while operating in harsh environments. Silicon Labs’ Digital Isolator Solutions Silicon Labs' digital isolators provide optimal solutions to the unique challenges of industrial environments. Our Si834x isolated smart switches are ideal for driving resistive and inductive loads, including solenoids, relays, and lamps commonly found in industrial control systems. They are fully compliant with IEC61131-2, so they interoperate well with other channels. Each switch can detect an open circuit condition and is protected against over-current, over-voltage from demagnetization (inductive kick or flyback voltage), and over-temperature conditions. An innovative multi-voltage smart clamp can manage an unlimited amount of demagnetization energy (EAS). Si834x switches are available in Parallel or SPI input types and sourcing or sinking output types. With substantial power savings and a compact 9x9 DFN package, these switches reduce board space and design headache!
Our Si838x isolated multi-channel input isolators are high-density, highly flexible devices that are ideal replacements for traditional optocouplers. They offer eight channels of 24 V digital field interface in a single compact QSOP package with integrated safety rated isolation. With a few external components, this structure provides compliance to IEC 61131-2 switch types 1, 2, or 3. The input interface is built on our ground-breaking CMOS-based LED emulator technology, which means the devices can handle sourcing or sinking configurations without a power supply on the field side. By utilizing our proprietary silicon isolation technology, these devices support up to 2.5 kV RMS withstand voltage, enabling high-speed capability, high noise immunity of 25 kV/µs, reduced variation with temperature and age, and better part-to-part matching. One Si838x isolator can replace eight traditional optocouplers, making them ideal solutions for space-constrained industrial facilities.
Watch these webinars to learn more about how our digital isolators provide optimal solutions to the unique challenges and harsh conditions of industrial environments: Protecting 24 V Digital Outputs and Factories are Dirty. To learn more about our Si834x and Si838x devices, contact your Silicon Labs sales representative. |
Mar 17 2021, 4:39 PM |
|
Tracy Boyd
|
Updated
Factories are Dirty: How to Protect 24 V Digital Inputs & Outputs in Industrial Environments on Blog
Industrial environments demand a lot from control systems. Devices such as programmable logic controllers (PLCs) must operate continuously with various components and as little maintenance and downtime as possible. However, a PLC is only as good as the input /output capabilities of the digital channels connected to the industrial ecosystem. Harsh, noisy environments and various unknown factors can all contribute to design challenges that affect digital channel reliability, resulting in possible circuit damage, downtime, and system failure. In the dual webinar sessions, Protecting 24 V Digital Outputs from the Unknown and Factories are Dirty – Protecting Industrial Digital Inputs, senior product manager Asa Kirby and applications engineers Travis Lenz and Kevin Huang describe the design challenges specific to industrial digital channels and how to mitigate them using Silicon Labs' Si834x and Si838x digital isolator devices. Environmental Challenges
Industrial ecosystems present a multitude of conditions that can result in damage to digital input and output channels. The most common challenges include:
Input/output-specific challenges include managing overload conditions and driving inductive loads for outputs and device compatibility and assembly/installation protection for inputs. Industrial systems must be able to handle all these varied design challenges while operating in harsh environments. Silicon Labs’ Digital Isolator Solutions Silicon Labs' digital isolators provide optimal solutions to the unique challenges of industrial environments. Our Si834x isolated smart switches are ideal for driving resistive and inductive loads, including solenoids, relays, and lamps commonly found in industrial control systems. They are fully compliant with IEC61131-2, so they interoperate well with other channels. Each switch can detect an open circuit condition and is protected against over-current, over-voltage from demagnetization (inductive kick or flyback voltage), and over-temperature conditions. An innovative multi-voltage smart clamp can manage an unlimited amount of demagnetization energy (EAS). Si834x switches are available in Parallel or SPI input types and sourcing or sinking output types. With substantial power savings and a compact 9x9 DFN package, these switches reduce board space and design headache!
Our Si838x isolated multi-channel input isolators are high-density, highly flexible devices that are ideal replacements for traditional optocouplers. They offer eight channels of 24 V digital field interface in a single compact QSOP package with integrated safety rated isolation. With a few external components, this structure provides compliance to IEC 61131-2 switch types 1, 2, or 3. The input interface is built on our ground-breaking CMOS-based LED emulator technology, which means the devices can handle sourcing or sinking configurations without a power supply on the field side. By utilizing our proprietary silicon isolation technology, these devices support up to 2.5 kV RMS withstand voltage, enabling high-speed capability, high noise immunity of 25 kV/µs, reduced variation with temperature and age, and better part-to-part matching. One Si838x isolator can replace eight traditional optocouplers, making them ideal solutions for space-constrained industrial facilities.
Watch these webinars to learn more about how our digital isolators provide optimal solutions to the unique challenges and harsh conditions of industrial environments: Protecting 24 V Digital Outputs and Factories are Dirty. To learn more about our Si834x and Si838x devices, contact your Silicon Labs sales representative. |
Mar 17 2021, 4:39 PM |
|
Tracy Boyd
|
Updated
What are the Top Isolated Gate Driver and Switch Considerations for Robust High-Power Inverters? on Blog
From the types of power switches you use to the layout of your printed circuit board (PCB), numerous design decisions will affect the robustness of your high-power inverter designs. In this Power Hour webinar, Staff Product Manager, John Wilson, and Sr. Staff Applications Engineer, Long Nguyen, describe the key issues and solutions to consider when designing high-power inverter systems. They introduce the Si828x isolated gate drivers and explain how they can benefit your high-power designs. The following highlights are some key takeaways from the presentation. One of the first decisions to make when designing your high-power inverters is the type of power switch you will use. Power switches have unique capabilities and requirements, such as voltage limits, temperature ranges, and operating frequencies, that will drive numerous design decisions for your high-power inverters, including which type of gate driver to use. The four main types of power switches are:
Working voltages are another essential factor to consider. Designers must evaluate the maximum voltages the system will be exposed to under normal conditions and ensure that the gate drivers and power switches can meet these power requirements. For the gate driver, the working voltage rating will exceed maximum expected peak voltages. For switches, a rule of thumb is that the maximum expected voltages should be less than 80% of the device family’s voltage rating. 
Gate drivers and power switches have critical protection needs that must be addressed in the design. For example, undervoltage issues generate heat and efficiency loss. Overvoltage can cause switch damage. Fortunately, these issues can be mitigated with solutions such as desaturation detection, using a Miller clamp to prevent switch parasitic turn-on, and careful PCB layout techniques. There are also application dependencies to consider. For example, a stable, high-power application, such as a steady-running industrial motor inverter, may not need much protection. In contrast, a dynamic application, such as an EV traction inverter, may require extensive system protection. PCB board layout is also an important consideration when designing a power electronic circuit because it determines the power circuit's performance, efficiency, and reliability. A well-planned PCB layout minimizes parasitic inductance and capacitance and improves reliability and efficiency. 
A final consideration is determining how to supply power to the secondary side of a half-bridge device. This task can be accomplished discreetly or in an integrated fashion. As you design your high-power inverters, look for power switch technologies and gate drivers appropriate to the working voltages required by your system application. Consider the critical protection needs and choose gate drivers that can provide solutions accordingly. Silicon Labs offers a full spectrum of solutions with our Si828x isolated gate drivers. An integrated dc-dc converter within these devices simplifies layout and provides each driver with its own power supply, which translates to reduced noise and inductances and a more compact and smaller PCB. 
The Si8285 has all the apps and features of the Si828x family (desaturation detection, Miller clamp, etc.), as well as an industry-leading noise immunity of 125 kV/us. We also have a robust reference circuit that enables adjusting various parameters based on the type of power switch you are using. 
In addition to the Si828x series, we offer an extensive isolated gate driver product family that is suitable for inverters. Altogether, these devices offer a broad range of benefits, from power robustness to extensive flexibility. 
Register here to watch the full webinar, which includes detailed examples. For more information about our isolated gate drivers, contact your Silicon Labs sales representative. |
Feb 03 2021, 6:49 PM |
|
Tracy Boyd
|
Posted
What are the Top Isolated Gate Driver and Switch Considerations for Robust High-Power Inverters? on Blog
From the types of power switches you use to the layout of your printed circuit board (PCB), numerous design decisions will affect the robustness of your high-power inverter designs. In this Power Hour webinar, Staff Product Manager, John Wilson, and Sr. Staff Applications Engineer, Long Nguyen, describe the key issues and solutions to consider when designing high-power inverter systems. They introduce the Si828x isolated gate drivers and explain how they can benefit your high-power designs. The following highlights are some key takeaways from the presentation. One of the first decisions to make when designing your high-power inverters is the type of power switch you will use. Power switches have unique capabilities and requirements, such as voltage limits, temperature ranges, and operating frequencies, that will drive numerous design decisions for your high-power inverters, including which type of gate driver to use. The four main types of power switches are:
Working voltages are another essential factor to consider. Designers must evaluate the maximum voltages the system will be exposed to under normal conditions and ensure that the gate drivers and power switches can meet these power requirements. For the gate driver, the working voltage rating will exceed maximum expected peak voltages. For switches, a rule of thumb is that the maximum expected voltages should be less than 80% of the device family’s voltage rating.
Gate drivers and power switches have critical protection needs that must be addressed in the design. For example, undervoltage issues generate heat and efficiency loss. Overvoltage can cause switch damage. Fortunately, these issues can be mitigated with solutions such as desaturation detection, using a Miller clamp to prevent switch parasitic turn-on, and careful PCB layout techniques. There are also application dependencies to consider. For example, a stable, high-power application, such as a steady-running industrial motor inverter, may not need much protection. In contrast, a dynamic application, such as an EV traction inverter, may require extensive system protection. PCB board layout is also an important consideration when designing a power electronic circuit because it determines the power circuit's performance, efficiency, and reliability. A well-planned PCB layout minimizes parasitic inductance and capacitance and improves reliability and efficiency.
A final consideration is determining how to supply power to the secondary side of a half-bridge device. This task can be accomplished discreetly or in an integrated fashion. As you design your high-power inverters, look for power switch technologies and gate drivers appropriate to the working voltages required by your system application. Consider the critical protection needs and choose gate drivers that can provide solutions accordingly. Silicon Labs offers a full spectrum of solutions with our Si828x isolated gate drivers. An integrated dc-dc converter within these devices simplifies layout and provides each driver with its own power supply, which translates to reduced noise and inductances and a more compact and smaller PCB.
The Si8285 has all the apps and features of the Si828x family (desaturation detection, Miller clamp, etc.), as well as an industry-leading noise immunity of 125 kV/us. We also have a robust reference circuit that enables adjusting various parameters based on the type of power switch you are using.
In addition to the Si828x series, we offer an extensive isolated gate driver product family that is suitable for inverters. Altogether, these devices offer a broad range of benefits, from power robustness to extensive flexibility.
Register here to watch the full webinar, which includes detailed examples. For more information about our isolated gate drivers, contact your Silicon Labs sales representative. |
Feb 03 2021, 6:49 PM |
|
Tracy Boyd
|
Updated
What are the Top Isolated Gate Driver and Switch Considerations for Robust High-Power Inverters? on Blog
From the types of power switches you use to the layout of your printed circuit board (PCB), numerous design decisions will affect the robustness of your high-power inverter designs. In this Power Hour webinar, Staff Product Manager, John Wilson, and Sr. Staff Applications Engineer, Long Nguyen, describe the key issues and solutions to consider when designing high-power inverter systems. They introduce the Si828x isolated gate drivers and explain how they can benefit your high-power designs. The following highlights are some key takeaways from the presentation. One of the first decisions to make when designing your high-power inverters is the type of power switch you will use. Power switches have unique capabilities and requirements, such as voltage limits, temperature ranges, and operating frequencies, that will drive numerous design decisions for your high-power inverters, including which type of gate driver to use. The four main types of power switches are:
Working voltages are another essential factor to consider. Designers must evaluate the maximum voltages the system will be exposed to under normal conditions and ensure that the gate drivers and power switches can meet these power requirements. For the gate driver, the working voltage rating will exceed maximum expected peak voltages. For switches, a rule of thumb is that the maximum expected voltages should be less than 80% of the device family’s voltage rating.
Gate drivers and power switches have critical protection needs that must be addressed in the design. For example, undervoltage issues generate heat and efficiency loss. Overvoltage can cause switch damage. Fortunately, these issues can be mitigated with solutions such as desaturation detection, using a Miller clamp to prevent switch parasitic turn-on, and careful PCB layout techniques. There are also application dependencies to consider. For example, a stable, high-power application, such as a steady-running industrial motor inverter, may not need much protection. In contrast, a dynamic application, such as an EV traction inverter, may require extensive system protection. PCB board layout is also an important consideration when designing a power electronic circuit because it determines the power circuit's performance, efficiency, and reliability. A well-planned PCB layout minimizes parasitic inductance and capacitance and improves reliability and efficiency.
A final consideration is determining how to supply power to the secondary side of a half-bridge device. This task can be accomplished discreetly or in an integrated fashion. As you design your high-power inverters, look for power switch technologies and gate drivers appropriate to the working voltages required by your system application. Consider the critical protection needs and choose gate drivers that can provide solutions accordingly. Silicon Labs offers a full spectrum of solutions with our Si828x isolated gate drivers. An integrated dc-dc converter within these devices simplifies layout and provides each driver with its own power supply, which translates to reduced noise and inductances and a more compact and smaller PCB.
The Si8285 has all the apps and features of the Si828x family (desaturation detection, Miller clamp, etc.), as well as an industry-leading noise immunity of 125 kV/us. We also have a robust reference circuit that enables adjusting various parameters based on the type of power switch you are using.
In addition to the Si828x series, we offer an extensive isolated gate driver product family that is suitable for inverters. Altogether, these devices offer a broad range of benefits, from power robustness to extensive flexibility.
Register here to watch the full webinar, which includes detailed examples. For more information about our isolated gate drivers, contact your Silicon Labs sales representative. |
Feb 03 2021, 6:49 PM |
|
Tracy Boyd
|
Updated
What are the Top Isolated Gate Driver and Switch Considerations for Robust High-Power Inverters? on Blog
From the types of power switches you use to the layout of your printed circuit board (PCB), numerous design decisions will affect the robustness of your high-power inverter designs. In this Power Hour webinar, Staff Product Manager, John Wilson, and Sr. Staff Applications Engineer, Long Nguyen, describe the key issues and solutions to consider when designing high-power inverter systems. They introduce the Si828x isolated gate drivers and explain how they can benefit your high-power designs. The following highlights are some key takeaways from the presentation. One of the first decisions to make when designing your high-power inverters is the type of power switch you will use. Power switches have unique capabilities and requirements, such as voltage limits, temperature ranges, and operating frequencies, that will drive numerous design decisions for your high-power inverters, including which type of gate driver to use. The four main types of power switches are:
Working voltages are another essential factor to consider. Designers must evaluate the maximum voltages the system will be exposed to under normal conditions and ensure that the gate drivers and power switches can meet these power requirements. For the gate driver, the working voltage rating will exceed maximum expected peak voltages. For switches, a rule of thumb is that the maximum expected voltages should be less than 80% of the device family’s voltage rating.
Gate drivers and power switches have critical protection needs that must be addressed in the design. For example, undervoltage issues generate heat and efficiency loss. Overvoltage can cause switch damage. Fortunately, these issues can be mitigated with solutions such as desaturation detection, using a Miller clamp to prevent switch parasitic turn-on, and careful PCB layout techniques. There are also application dependencies to consider. For example, a stable, high-power application, such as a steady-running industrial motor inverter, may not need much protection. In contrast, a dynamic application, such as an EV traction inverter, may require extensive system protection. PCB board layout is also an important consideration when designing a power electronic circuit because it determines the power circuit's performance, efficiency, and reliability. A well-planned PCB layout minimizes parasitic inductance and capacitance and improves reliability and efficiency.
A final consideration is determining how to supply power to the secondary side of a half-bridge device. This task can be accomplished discreetly or in an integrated fashion. As you design your high-power inverters, look for power switch technologies and gate drivers appropriate to the working voltages required by your system application. Consider the critical protection needs and choose gate drivers that can provide solutions accordingly. Silicon Labs offers a full spectrum of solutions with our Si828x isolated gate drivers. An integrated dc-dc converter within these devices simplifies layout and provides each driver with its own power supply, which translates to reduced noise and inductances and a more compact and smaller PCB.
The Si8285 has all the apps and features of the Si828x family (desaturation detection, Miller clamp, etc.), as well as an industry-leading noise immunity of 125 kV/us. We also have a robust reference circuit that enables adjusting various parameters based on the type of power switch you are using.
In addition to the Si828x series, we offer an extensive isolated gate driver product family that is suitable for inverters. Altogether, these devices offer a broad range of benefits, from power robustness to extensive flexibility.
Register here to watch the full webinar, which includes detailed examples. For more information about our isolated gate drivers, contact your Silicon Labs sales representative. |
Feb 03 2021, 6:49 PM |
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