I need some clarification on I/O vs. core voltages for the Si5330F device-
Requirements are one input clock (25 Mhz) at either 1.8V or 3.3V (3.3V is preferred for availability) and output CMOS single ended clocks at 1.8V, 2.5V, and 3.3V. According to the knowledge base notes on this kind of application, I will need to use the Si5330F-B00216-GM 1.8V device since 1.8V is the lowest output voltage requirement (note says must stay within 70% of expected VDDO). Can this device be powered with Vdd=3.3V, so that I can use the 3.3V input clock source for availability reasons? Or will I have to use a 1.8V input source and set the VDDcore=1.8V? Any better combinations?
This is a quick turn issue, so need an available solution very short turn.
You can use VDD = 3.3V with VDDO = 1.8V.
Please ensure that input clock meets the VIH requirements for this 3.3V VDD.
The outputs will have a swing of 1.8V since they are powered by a 1.8V standard at VDDO.