Understanding the Digital Hold feature in the Si5324.
I am using the Si5324 part for generating a clock from an input reference clock signal. input reference clock signal is coming from a tri-level generator at 59.94Hz or 60.00Hz. The desire is to lock the Si5324 part at frequency (59.94 or 60) and regardless if the input frequency changes the locked frequency will not change.
The input frequency is selected and the Si5324 is locked. I write the value: 0010 0101 to register 3 to
force the part into digital hold. However when I switch the input frequency the Si5324 also changes to the new frequency. What am I missing on how DHOLD functions or how to properly enable this feature?
An Si5324 EVB was set up in the lab and we see holdover when reg 03 = 15h, an input frequency change does not affect holdover. Can you read register 03 afterwards, say after it appears to relock to the new input frequency.
Thanks for feedback
Thank you for the response.
We preformed the experiment again this afternoon with a frequency of 59.94Hz input. Register responded with a 15h value. We then transmitted a 35h value to resister 3 writing DHOLD high. The input frequency was changed to 60.00Hz and the output frequency did not change and maintained the preciously locked 59.94Hz.
I feel the Si5324 part is functioning as described.
Again, Thank you
Thanks for feedback, good luck on the project