Our application uses the CLK0 and CLK1 outputs of a 5351A chip (on a third party PCB) as local oscillators in our ham radio application. These clocks operate at 106.8 MHz and 107.4 MHz, with a reference clock of 19.2 MHz driving the PLL X0 input. We are seeing very high spur content from both of the clock outputs, despite efforts to implement integer division synthesis in the PLL feedback loop as well as in the output clock divider chains. We are using an Arduino Pro Mini to program the 5351A (see the hardware photo).
The 2nd and 3rd photos shows the spectrum from one of the clock outputs. The first of these was obtained using a 19.2 MHz clock with the PLL feedback integer mode disabled and the 2nd obtained with a 4.8 MHz clock with PLL feedback integer mode enabled (106.8 MHz x 8 and 107.4 MHz x 8 are both integer multiples of 4.8 MHz). The Arduino programming file used to obtain each of these photos (with the same filename) is also shown for reference. We are constrained to use a 19.2 MHz clock or some integer divisor of it by its use elsewhere in our radio system.
Could someone please advise me what might be wrong?
Thank you very much!
Oliver Barrett KB6BA