I have inherited a design with the following Frequency Plan but without any commentary or explanation:
CKIN1 = 27MHz (Generated as hi 6.37ns, lo 33.67ns, hi 6.73ns, lo 26.93ns, repeat. Thus there is regular jitter of 6.74ns p-p at 13.5MHz.)
N31 = 14
N2_HS = 11
N2_LS = 254
N1_HS = 6
NC1_LS = 6
BW= 8 (BWSEL_REG = 10)
Of the thirty or so production items that have been built, about ten show reluctance for the Si5324 to lock to the 27MHz input. Mostly this is a problem only at cold (-20C), but some do not lock even at room temperature.
I took one production item that had never locked, even at room temperature, and fed it a jitter-free 27MHz. It locked every time. Thus it seems that it does not like the jitter.
My questions are:
Is the low value of N31 a problem in that it presumably passes a 6.74ns p-p jitter at 964kHz into the DSPLL?
Would a higher value of N31 be of benefit?
Would the associated higher value of N2 then be a problem?
After a bit more thinking, I have another question:
Does the even value (14) of N31 mean that for the CKIN1 described there should be zero regular jitter at the input to the DSPLL?
The biggest lock issue with Si5324 has been the LOCKT setting is not optimized, a 0x4 setting is usually best. What is the current LOCKT setting?
LOCKT is 0x1. Maybe the recommendation of para 126.96.36.199 of the Reference Manual was being followed.