The cover of the data sheet indicates the part drives 12 LVCMOS outputs. Are these all the same phase (assuming I select single-ended SFOUTs), or are 6 of them 180-degrees away from the other 6? I haven't found any specific mention of this. There's an indirect implication in the section on synchronous output enables, which conflicts with the terse verbiage in the pin descriptions.
Separately, I'm expecting to input LVDS, and drive LVCMOS. Should I be reading anything into the absence of that combination in the additive jitter tables?
Thanks for any answers.
All LVCMOS outputs are in-phase.
There's no particular reason we don't have a differential input to single-ended output additive table other than it's not a typical application configuration. We do show single-ended input to single-ended LVCMOS output additive jitter, and using this table should give a good approximation of additive jitter for your LVDS input to LVCMOS output configuration.