I have not found any information containing the jitter propagation from i.e. a TCXO (having 5ps RMS jitter).
My question is will I have at the output of the SI5334 1ps RMS jitter as specified in the datasheet of the SI5334 or will both RMS values add?
I need for a ADC application a clock with <=1ps RMS jitter and LVDS output. Hope someone can help me.
The additive jitter calculation using RMS jitter values applies to non-PLL buffers becuase their noise transfer is treated as addition of white noise only.
PLLs have their own noise transfer function.
Hence we need a "convolution" of input and output jitter.
I have attached an illustration of the jitter to expect based on the input jitter to Si5334.
Therefore if the input jitter is 5 ps RMS, please find the integration BW.
Also, please ensure that the integration BW includes the nyquist rate for your ADC (or a apply a corresponding scaling if your ADC is oversampled).
In general, if you apply this TCXO to Si5334, the output is likely to violate the ADC jitter requirement.
There are two options:
1. Choose a higher performance TCXO as reference to Si5334 so that the output meets the ADC requirement.
2. Choose Si5319, our one output JITTER ATTENUATOR which will be able to filter the TCXO jitter and provide an output complaint with the ADC requirement.
Also, please ensure that the clock spurs will meet your ADC's SFDR requirements. You can do so by requesting a phase noise plot from us (SiLabs) after you have finalized the part and the input clock.