Hello guys, good morning.
I have already post this message weeks ago, but it didn't receive any answer.
I post again now here, explaining the question better.
My apologies if this will annoy you. Of course this is last time I post this.
I'm using Si5351A for transmitting on 14 MHz frequency. This chip has 3 clocks (CLK0, CLK1 and CLK2).
I would kindly ask you if it is possible to transmit (generate clock signal) at same time on three different frequencies, e.g. 14097000, 14097100 and 14097200 Hz, or anyhow three different frequencies everytime in a range of 200 Hz, no more. Has anyone tried to do this?
Thank you so much for your appreciated help.
You would need to try that, for your use case, the values enter ok and report like this
PLL_A: Enabled Features = None Fvco = 898.6965 MHz M = 34.56525 Input0: Source = Crystal Source Frequency = 26 MHz Fpfd = 26 MHz Load Capacitance = Load_08pF Output0: Features = None Disabled State = StopLow R = 1 (2^0) Fout = 14.097 MHz N = 63.7509044477548414... [ 63 + 7057/9398 ] Output1: Features = None Disabled State = StopLow R = 1 (2^0) Fout = 14.0971 MHz N = 63.7504522206694994... [ 63 + 105792/140971 ] Output2: Features = None Disabled State = StopLow R = 1 (2^0) Fout = 14.0972 MHz N = 63.75
but notice they have a common VCO and varying fractional feedback dividers.
The fraction of 105792/140971 means the average value will be precise for 10ms multiple windows, but will have jitter in shorter windows,
Manual force to use two PLLs may give better results, and using 2 Si5351A's may be an option, that would be easy enough to try and compare ?