I have been using si5324 for as jiiter attenuator for STM-16/64 line cards and now I am trying to use the same for STM-1/4 line cards.But I am facing jitter tolerance issue for STM-1 signal.
Si5324 datasheet has mentioned that it supports STM-16/64 data rates. Is there a way to meet the jitter tolerance requirement of STM -1 signals using SI5324 ?
Could you elaborate on the "issue" more?
1. what is your system setup? what XTAL are you using? what is the frequency plan and your bandwidth settings?
2. How are you running the jitter tolerance test?
3. Which frequency range failed? by how much?
1. The system setup is using a CDR inside FPFA to recover STM -1/4 clock form the data. This recovered clock is then send to SI5324 for jitter cleaning purpose. Finally the cleaned clock is being used for further processing of data. In free running mode 114 MHz clock is being used. I have attached the PLL settings file for your reference.
2. I am using JDSU ONT600 to perform the jitter tolerance test.
3. Please find the attached results on one of the cards for STM -1. The frequnecy range where it is failing is 150KHz to 5500KHz.
Thanks for sending me those files. I have some follow up questions:
1. Are you using XTAL or external reference clock for the 114MHz clock? if external reference, have you checked the quality of that signal? phase noise for example? Because it will have a big impact on the the output jitter/phase noise
2. What does the jitter tolerance test do in more details? I found the limit table in ITU-T G.825, but I don't quite understand the test. How does JDSU run the test? is it SJ only? what is the SJ amplitude?
3. I don't quite understand the test result. Blue dots were missing where you call out "Fail". Where are those blue dots for those frequencies? You mentioned that it passed STM-16 right? can you send me a image of passed test result?
Sorry for the late response.
Please find the answers below.
1) I am using XTAL for 114 MHz clock. But during jitter tolerance test clkin1 ( recovered clock from the data) is used for clock generation. I have not done any quality check on this clock.
2) Unfortunately even I don't have much idea about it. I connect the input/output port of my card to instrument and start the test. Same way I have done for STM-16/STM-64 cards where I see jitter tolerance test passing. I am not sure what SJ means?? Amplitude level is not shown in the instrument in case card fails the test.
3) Yes the points where blue dots are missing is the region if jitter frequnect where cards fail the jitter test. Please find the attached report for STM-16 card.
Do you have that report for STM-1 ?
Please find the attached report.
Have you rerun the test multiple times? Did it always fail at 600KHz? and was the result always 0.149 UI ?
Could you rerun it multiple times and send me the reports? It is weird that only one frequency failed.
I also recommend you to run the jitter test again with a known good 100MHz as input, instead of the recovered clock, and see if the same frequency fails.
sorry, input is 38.88MHz in your setup
The issue has been resolved. The recovered clock to the PLL was not of good quality. I changed the recovered clock quality now its working fine.
Thanks for the help.
Glad that it worked. Just curious, how do you improve the recovered clock quality? was it signal integrity issue? or did you tweak some of the equalizer settings?
I had to change my clock data recovery design to get the desired results.