The Si534x/7x/8x/9x clock generators and jitter attenuators can generate clocks compatible with HCSL receivers. However, the designer must be careful not to use conventional HCSL termination networks but rather follow the recommended HCSL termination in the reference manual.
Conventional HCSL relies on steering a 15mA current across two 50 ohm resistors to ground, which generates the high and low levels of roughly 750mV and 0mV respectively. In contrast, the Si534x/7x/8x/9x driver generates the proper HCSL voltage swing on the driver side and then AC couples that signal to a 50 ohm (Thevenin) resistor divider network to set the proper HCSL common-mode level of about 0.375V at the receiver side.
Figure 1 shows proper HCSL termination for Si534x/7x/8x/9x devices, copied from the reference manual. Figures 2-4 show examples of commonly used HCSL termination networks which should not be used for Si53x4/x7/x8/9x devices.
*Please note that other product families in the Silabs timing portfolio may have different methods of terminating HCSL clocks, and the documentation will provide the proper termination network.
Proper HCSL Termination Networks
Examples of Improper HCSL Termination Networks
In this article, an input is considered unused when that input is declared as “Unused (Powered-down)” in ClockBuilder Pro.
An active clock signal on an unused input must not violate the maximum and minimum voltage level at the input pins, which are +3.8V and -1.0V respectively. Permanent device damage may occur if the absolute maximum ratings are exceeded. If the unused input is AC coupled, then input pin will be biased at 0V. Therefore, the maximum peak-to-peak swing of the AC coupled input must not be greater than 2Vpp [0V – 2Vpp/2 = -1V] so that the signal does not fall below -1.0V. See below figure for example scenarios.
It is okay to provide an active clock signal to an unused input if:
It is not okay to provide an active clock signal to an unused input if:
Whether an input is unused or enabled, the absolute maximum/minimum ratings cannot be violated. The designer must take into account any overshoot/undershoot in the signal, any temperature related effects that could cause increased overshoot/undershoot, or any uncertainty in the signal amplitude. It is always advised to leave some margin to minimize potential risks.
A HCSL clock can be applied at IN2, IN1, or IN0 of Si5341. Regarding to the termination, just use an AC blocking cap in series with each input. This is present a high impedance to the PCB trace and should be what the customer needs since they have source side impedance matching. You can remove the 100 Ohm resistor between IN+ and IN- if the source is terminated properly.
Or you can put the 100 Ohm resistor on the other side of the AC coupling caps but keep the 100 Ohm resistor within 5 mm of the input pins.
Package: All devices with the QFN packages use NiPdAu plating.
Thickness: Following table gives details about the thickness of different materials:
Flash (<<0.1 µin)
Devices: All the devices from the Si534x (Si5340/41/42/44/45/46/47/48) family, the external crystal devices from the Si539x (Si5391/92/94/95/96/97) family and the Si5381/82/86 devices have the above terminal finish.
Package: All devices with the LGA packages use the Electroplated Ni/Au plating.
Thickness: Following table gives details about the thickness of different materials:
Devices: The integrated crystal devices from the Si539x (Si5392/94/95/95/97) and the Si5383/83/88/89 devices have the above terminal finish.
If more details are required regarding device composition, please refer our RFI portal. Following are the steps to access the same:
Now if the information you need is not present there, then you have to create a support request using the following link:
See attached PDF for articles:
1 Adjusting the PPS out
2 Are PTP Unicast packets visible to Wireshark through a switch?
3 Are there any important parameters that should be taken into account when choosing a network switch chip to connect to the M88?
4 Can the module be synchronized to an input 1PPS without having a ToD input from the GPS?
5 Difference Between Engine Asymmetry and Port Asymmetry settings?
6 Do the modules support IGMP?
7 Does the AccuTime module have an SNTP server available?
8 Energy Efficient Ethernet
9 Ethernet LED meaning
10 How can 1PPS be enabled for syntonization from GPS when ToD is not available?
11 How can files be transferred to/from a AccuTime module file system from a host PC/laptop?
12 How can I tell that the slave is Synchronized to the master?
13 How can Clock Class during Holdover be set by CLI Commands?
14 How do I get firmware updates?
15 How do AccuTime modules communicate with external PHY?
16 How is checksum handled for IPv4 and IPv6?
17 How many clients does your master support?
18 How many other slaves can your slave handle?
19 How much does the modules weigh?
20 How much time does it take to synchronize?
21 How to interpret the sync status
22 How to transfer files using kermit on a Linux machine
23 Is a '00' Master Clock ID valid for an AccuTime module slave to sync to?
24 Is defining a fixed PPSOUT/FREQOUT relationship that is the same every time the M64 is restarted possible?
25 M88 CLK_REF specification
26 Running PTP over Ethernet (layer 2) on enet1
27 Setting DSCP for PTP
28 The two interfaces of M64 and M68
29 There is a 3 µs offset between master and slave's 1PPS. What do I do?
30 There is a leap second announced. What do I do?
31 What are some guidelines for the "ptp2 config" parameters for servo control?
32 What are the set up conditions required to get TOD outputs to activate on the module?
33 What are the Synchronization Requirements for Different Types of LTE?
34 What does the console output data represent when the module is run in Mode 4 (Debug)?
35 What is a guideline for setting the GPS Antenna cable delay value?
36 What is the command procedure to upload an module file to a PC using Kermit?
37 What is the difference between congruent and non-congruent mode when operating the M88 module?
38 What is the Ether type for Layer 2 and Layer 3 communication protocol?
39 What is the maximum overlap/delay that is acceptable for a AccuTime timing module between the TOD and the 1PPS input?
40 What is the module ToD interface and format?
41 What is the normal boot process for the modules?
42 What is the recommended power sequencing for M88?
43 What is the Re-flow profile required for M6x module?
44 What NMEA messages are used for TOD input and output?
45 What PTP switches can be used with the AccuTime module IEEE 1588-2008 equipment?
46 What the preferred PTP Engine Mode for a module Clock with multiple PTP ports and configured as a Boundary Clock or Gateway Clock when the Primary Timing Source is GPS?
47 What time scale is used by PTP and what is the relationship to other time scales?
48 What's the difference between a one-step master and a two-step master?
49 What's the maximum operating temperature for M64/M68?
50 What's the MTBF for M88
51 Why are there 4 bytes after the PTP message?
52 What happened to support for the M50 and the development kit.
53 Revision History
Note: 1. Check or uncheck the boxes won’t change the chip state machine, INTRb will only indicate the checked detections. 2. INTRb is the NOR of flags and those flags need to be cleared manually by writing 0x0 to the corresponded _FLGs. 3. The last input rise edge to INTRb negative edge is 2.15us but not exact 4 Fpfd cycles (Fpfd = 2MHz that is T = 500ns period) due to internal delay.
Typically, /CS pin of Si534x/8x/9x SPI should be pulled up to be High (logic 1) between each two bytes transfer for reliability. In case of rare alignment issues, setting /CS high will help the SPI logic to recover by reinitializing its state machine. An example timing diagram of issuing the pulse of /CS is shown as below:
An example brief timing diagram of /CS pulse sequences is shown in the below figure. The left sequence is recommended for Si534x/8x/9x SPI; the right one may work to achieve several transfers of more than two bytes while /CS is kept as low. However, it is the responsibility of the user to test sufficiently to ensure SPI communication reliability.
Si5348 have 3 output enable pins, i.e. OE0b, OE1b and OE2b. Those output enable pins can be mapped to control any of the outputs (OUTx) through the configuration steps below:
Step 1: Set 0x0022h = 0 to enable using OExb pins to control the outputs.
Step 2: Set the mask registers below to map the outputs to OExb pins.
OExb mask registers (above) are used to configure the outputs to be under control by OExb pins (logic 1) or not (logic 0), respectively. Note that the same bit of three OExb mask registers should not be set as 0 at the same time otherwise the corresponding output will be disabled no matter OExb pins inputs.
This is following the example mappings from the table above:
Example Out 0, Out 1, Out 2 controlled by OE0b pin.
Write 0x0023h = 0x38h
Write 0x0024h = 0x00h
Example Out3, Out4 and Out5 controlled by OE1b pin.
Write 0x0025h = 0x80h
Write 0x0026h = 0x03h
Example Out 6 controlled by OE2b pin.
Write 0x0027h = 0x00h
Write 0x0028h = 0x08h
1.1 Where can I get detailed material composition information on these devices?
1.2 Is the part RoHS compliant?
1.3 What is the Moisture Sensitivity Level (MSL) rating for the Si5388/89?
1.4 What is the recommend profile for solder reflow process?
2.1 Where can I find the IBIS model for the Si5388/89?
2.2 Do you have a list of recommended crystals?
2.3 I don’t want to use a crystal with the Si5388/89. Can I use an XO or TCXO as the XA/XB reference instead? And if so, how do I interface an external oscillator to the device?
3.1 What IEEE 1588 Profiles are included in the current solution
3.2 Does this solution meet ITU G.8262 for SyncE and G.8262.1 for Enhanced SyncE?
4.1 How do I get a complete evaluation system?
4.2 What software is available for the evaluation system
4.3 Why is a Xilinx FPGA evaluation board required?
4.4 My Xilinx Carrier Card (ZCU102 or ZCU111) is not passing self-test – what could be wrong?
5.1 What system architectures does this solution support?
5.2 What clock configurations does the Si5388/89 solution support?
6.1 Is a compliance report available?
6.2 What type of reference clocks can you provide G.8273.2 compliance reports for?
6.3 What class do you support for ITU-T G.8273.2 compliance?
7.1 What serial interfaces does the device support?
7.2 Does the Si5388/89 support Zero-Delay Mode?
7.3 Can the application FW and/or device configuration (i.e. Frequency Plan) be modified by the user independently and how is this done?
7.4 Are there any restrictions on which DSPLL can be used for IEEE 1588 synchronization?
8.1 What is the pull in range of the PTP loop and SyncE PLL?
8.2 Using the BMCA algorithm how long does it take to switch to a new master and what is the measurement criterion?
8.3 The cTE between my Master and Slave/Boundary Clock is very large - what could cause this?
8.4 How many slaves can this solution support and what are the dependent parameters?
8.5 What is DCO mode and how can it be exercised?
8.6 What OCXO vendor and part number do you recommend?
8.7 What type of reference oscillator should I use?
9.1 What operating system does the Si5388/89 solution run under?
9.2 What Linux kernel version does the SW use?
9.3 What modules does the SW in the Si5389 solution support?
9.4 What format is the SW delivered?
10.1 Can Silicon Labs provide source verilog files?
10.2 What Xilinx FPGA’s can Silicon Labs’ SW be ported to?
The clock generator devices like Si5340/41/91 as well as the jitter attenuator devices like Si5345/95 are both designed to provide low jitter output clocks. But a major difference is that the jitter attenuators, as the name suggests, will attenuate the noise/jitter at the input while for the clock generators, the noise at the input passes through to the output and contributes to the output jitter value.
Therefore, in case of the clock generator devices, the total RMS jitter at the output will tremendously depend on the jitter of the input source and also on the input frequency. In order to get the best jitter performance, it is recommended to use an input frequency between 48MHz to 54MHz at the XAXB pins of these devices and also to avoid using low frequencies like 20MHz or 25MHz at the input. Lower input frequencies cause an increase in noise at the clock output which is seen as increased RMS jitter.
The above applies to both the XAXB pins and the clock inputs pins for the clock generators.
Also, the signal generator or the oscillator used at the input should have minimum possible jitter. The Rohde & Schwarz SMA 100 signal generator is one of the very low jitter signal generators available
Now in case of the jitter attenuating clocks, any allowed input frequency and any signal generator can be used to produce the input signal and it will not have any effect on the output clock jitter.