Since power supply limitation, sometimes we need convert CMOS signal level to meet receiver requirement. Such as 3.3V to 2.5V, 1.8V to 1.2V
Please refer to below interfacing from AN408 for this conversion.
This resistor attenuator network should consider device source impedance Rs (usually this information can be found in datasheet). The R1 and R2 calculation should consider below two items:
1. R2 parallel with R1+ Rs to get 50 ohms resistor for impedance matching.
2. R2 /(R1+Rs) equal to ratio of receiver swing/ source swing
Attachment is one excel tool to calculate R1 and R2 according to source/receiver level and source impedance
In the Si5395-91 & Si5345-40 devices, DCO mode is intended to be used within the range of +/-350ppm. It is possible to use DCO mode beyond this range, but it is important to be aware of the following caveats:
where Fvco is the VCO frequency, NDEN is the N-divider denominator, NNUM is the N-divider numerator, NNUM,DELTA is the value which the numerator is being incremented/decremented by per step, X is the net amount of steps applied, and R is the integer R-divider value. If DCO mode is operated within a narrow frequency range, Fout has an approximately linear relation to X. However, as the frequency range increases, Fout becomes increasingly nonlinear with respect to X. Consequently, the actual frequency step size will be significantly different from the desired step size as the N-divider is continually incremented/decremented.
The following are the recommended solutions to address the above issues:
For more details on DCO mode and FOTF, please refer to the following application notes:
The Si534x/7x/8x/9x clock generators and jitter attenuators can generate clocks compatible with HCSL receivers. However, the designer must be careful not to use conventional HCSL termination networks but rather follow the recommended HCSL termination in the reference manual.
Conventional HCSL relies on steering a 15mA current across two 50 ohm resistors to ground, which generates the high and low levels of roughly 750mV and 0mV respectively. In contrast, the Si534x/7x/8x/9x driver generates the proper HCSL voltage swing on the driver side and then AC couples that signal to a 50 ohm (Thevenin) resistor divider network to set the proper HCSL common-mode level of about 0.375V at the receiver side.
Figure 1 shows proper HCSL termination for Si534x/7x/8x/9x devices, copied from the reference manual. Figures 2-4 show examples of commonly used HCSL termination networks which should not be used for Si53x4/x7/x8/9x devices.
*Please note that other product families in the Silabs timing portfolio may have different methods of terminating HCSL clocks, and the documentation will provide the proper termination network.
Proper HCSL Termination Networks
Examples of Improper HCSL Termination Networks
In this article, an input is considered unused when that input is declared as “Unused (Powered-down)” in ClockBuilder Pro.
An active clock signal on an unused input must not violate the maximum and minimum voltage level at the input pins, which are +3.8V and -1.0V respectively. Permanent device damage may occur if the absolute maximum ratings are exceeded. If the unused input is AC coupled, then input pin will be biased at 0V. Therefore, the maximum peak-to-peak swing of the AC coupled input must not be greater than 2Vpp [0V – 2Vpp/2 = -1V] so that the signal does not fall below -1.0V. See below figure for example scenarios.
It is okay to provide an active clock signal to an unused input if:
It is not okay to provide an active clock signal to an unused input if:
Whether an input is unused or enabled, the absolute maximum/minimum ratings cannot be violated. The designer must take into account any overshoot/undershoot in the signal, any temperature related effects that could cause increased overshoot/undershoot, or any uncertainty in the signal amplitude. It is always advised to leave some margin to minimize potential risks.
A HCSL clock can be applied at IN2, IN1, or IN0 of Si5341. Regarding to the termination, just use an AC blocking cap in series with each input. This is present a high impedance to the PCB trace and should be what the customer needs since they have source side impedance matching. You can remove the 100 Ohm resistor between IN+ and IN- if the source is terminated properly.
Or you can put the 100 Ohm resistor on the other side of the AC coupling caps but keep the 100 Ohm resistor within 5 mm of the input pins.
Package: All devices with the QFN packages use NiPdAu plating.
Thickness: Following table gives details about the thickness of different materials:
Flash (<<0.1 µin)
Devices: All the devices from the Si534x (Si5340/41/42/44/45/46/47/48) family, the external crystal devices from the Si539x (Si5391/92/94/95/96/97) family and the Si5381/82/86 devices have the above terminal finish.
Package: All devices with the LGA packages use the Electroplated Ni/Au plating.
Thickness: Following table gives details about the thickness of different materials:
Devices: The integrated crystal devices from the Si539x (Si5392/94/95/95/97) and the Si5383/83/88/89 devices have the above terminal finish.
If more details are required regarding device composition, please refer our RFI portal. Following are the steps to access the same:
Now if the information you need is not present there, then you have to create a support request using the following link:
See attached PDF for articles:
1 Adjusting the PPS out
2 Are PTP Unicast packets visible to Wireshark through a switch?
3 Are there any important parameters that should be taken into account when choosing a network switch chip to connect to the M88?
4 Can the module be synchronized to an input 1PPS without having a ToD input from the GPS?
5 Difference Between Engine Asymmetry and Port Asymmetry settings?
6 Do the modules support IGMP?
7 Does the AccuTime module have an SNTP server available?
8 Energy Efficient Ethernet
9 Ethernet LED meaning
10 How can 1PPS be enabled for syntonization from GPS when ToD is not available?
11 How can files be transferred to/from a AccuTime module file system from a host PC/laptop?
12 How can I tell that the slave is Synchronized to the master?
13 How can Clock Class during Holdover be set by CLI Commands?
14 How do I get firmware updates?
15 How do AccuTime modules communicate with external PHY?
16 How is checksum handled for IPv4 and IPv6?
17 How many clients does your master support?
18 How many other slaves can your slave handle?
19 How much does the modules weigh?
20 How much time does it take to synchronize?
21 How to interpret the sync status
22 How to transfer files using kermit on a Linux machine
23 Is a '00' Master Clock ID valid for an AccuTime module slave to sync to?
24 Is defining a fixed PPSOUT/FREQOUT relationship that is the same every time the M64 is restarted possible?
25 M88 CLK_REF specification
26 Running PTP over Ethernet (layer 2) on enet1
27 Setting DSCP for PTP
28 The two interfaces of M64 and M68
29 There is a 3 µs offset between master and slave's 1PPS. What do I do?
30 There is a leap second announced. What do I do?
31 What are some guidelines for the "ptp2 config" parameters for servo control?
32 What are the set up conditions required to get TOD outputs to activate on the module?
33 What are the Synchronization Requirements for Different Types of LTE?
34 What does the console output data represent when the module is run in Mode 4 (Debug)?
35 What is a guideline for setting the GPS Antenna cable delay value?
36 What is the command procedure to upload an module file to a PC using Kermit?
37 What is the difference between congruent and non-congruent mode when operating the M88 module?
38 What is the Ether type for Layer 2 and Layer 3 communication protocol?
39 What is the maximum overlap/delay that is acceptable for a AccuTime timing module between the TOD and the 1PPS input?
40 What is the module ToD interface and format?
41 What is the normal boot process for the modules?
42 What is the recommended power sequencing for M88?
43 What is the Re-flow profile required for M6x module?
44 What NMEA messages are used for TOD input and output?
45 What PTP switches can be used with the AccuTime module IEEE 1588-2008 equipment?
46 What the preferred PTP Engine Mode for a module Clock with multiple PTP ports and configured as a Boundary Clock or Gateway Clock when the Primary Timing Source is GPS?
47 What time scale is used by PTP and what is the relationship to other time scales?
48 What's the difference between a one-step master and a two-step master?
49 What's the maximum operating temperature for M64/M68?
50 What's the MTBF for M88
51 Why are there 4 bytes after the PTP message?
52 What happened to support for the M50 and the development kit.
53 Revision History
Note: 1. Check or uncheck the boxes won’t change the chip state machine, INTRb will only indicate the checked detections. 2. INTRb is the NOR of flags and those flags need to be cleared manually by writing 0x0 to the corresponded _FLGs. 3. The last input rise edge to INTRb negative edge is 2.15us but not exact 4 Fpfd cycles (Fpfd = 2MHz that is T = 500ns period) due to internal delay.
Typically, /CS pin of Si534x/8x/9x SPI should be pulled up to be High (logic 1) between each two bytes transfer for reliability. In case of rare alignment issues, setting /CS high will help the SPI logic to recover by reinitializing its state machine. An example timing diagram of issuing the pulse of /CS is shown as below:
An example brief timing diagram of /CS pulse sequences is shown in the below figure. The left sequence is recommended for Si534x/8x/9x SPI; the right one may work to achieve several transfers of more than two bytes while /CS is kept as low. However, it is the responsibility of the user to test sufficiently to ensure SPI communication reliability.
Si5348 have 3 output enable pins, i.e. OE0b, OE1b and OE2b. Those output enable pins can be mapped to control any of the outputs (OUTx) through the configuration steps below:
Step 1: Set 0x0022h = 0 to enable using OExb pins to control the outputs.
Step 2: Set the mask registers below to map the outputs to OExb pins.
OExb mask registers (above) are used to configure the outputs to be under control by OExb pins (logic 1) or not (logic 0), respectively. Note that the same bit of three OExb mask registers should not be set as 0 at the same time otherwise the corresponding output will be disabled no matter OExb pins inputs.
This is following the example mappings from the table above:
Example Out 0, Out 1, Out 2 controlled by OE0b pin.
Write 0x0023h = 0x38h
Write 0x0024h = 0x00h
Example Out3, Out4 and Out5 controlled by OE1b pin.
Write 0x0025h = 0x80h
Write 0x0026h = 0x03h
Example Out 6 controlled by OE2b pin.
Write 0x0027h = 0x00h
Write 0x0028h = 0x08h
The clock generator devices like Si5340/41/91 as well as the jitter attenuator devices like Si5345/95 are both designed to provide low jitter output clocks. But a major difference is that the jitter attenuators, as the name suggests, will attenuate the noise/jitter at the input while for the clock generators, the noise at the input passes through to the output and contributes to the output jitter value.
Therefore, in case of the clock generator devices, the total RMS jitter at the output will tremendously depend on the jitter of the input source and also on the input frequency. In order to get the best jitter performance, it is recommended to use an input frequency between 48MHz to 54MHz at the XAXB pins of these devices and also to avoid using low frequencies like 20MHz or 25MHz at the input. Lower input frequencies cause an increase in noise at the clock output which is seen as increased RMS jitter.
The above applies to both the XAXB pins and the clock inputs pins for the clock generators.
Also, the signal generator or the oscillator used at the input should have minimum possible jitter. The Rohde & Schwarz SMA 100 signal generator is one of the very low jitter signal generators available
Now in case of the jitter attenuating clocks, any allowed input frequency and any signal generator can be used to produce the input signal and it will not have any effect on the output clock jitter.
Frequency accuracy is an important parameter when selecting a reference clock for any application. In general frequency accuracy is the difference in the measured value of the crystal/XO/TCXO/OCXO frequencies from the ideal expected value.
Following factors contribute to the accuracy measurement:
Frequency of a crystal/XO/TCXO/OCXO is measured after placing the device in a temperature-controlled chamber and then varying the temperature from -40°C to 85°C. Then the frequency accuracy at a particular temperature is calculated in ppm as follows:
Facc = Frequency accuracy at particular temperature
Ft = Frequency at particular temperature
Fref = Frequency at 25°C
This Ref freq can be calculated using any of the following two techniques (this is usually specified in the datasheet for the device):
DCO mode allows the user to dynamically change an output clock frequency in any existing device or OPN if required. The output frequency can be modifying by changing the N divider value which is assigned to the particular clock output. However manually writing to the N dividers is not a recommended way to use the DCO mode. There are certain factors which need to be considered.
The N divider which is associated with the DCO enabled output should be in fractional mode. If the N divider is integer in the original project file, then it needs to be changed to operate in the fractional mode. The register PIBYP[4:0] enables to change the N divider mode. Each bit in this register is assigned to one N divider. If N0 needs to be in fractional mode, write 0 to PIBYP. Note that a soft reset should be performed after changing the above mentioned register.
The next step involves calculating the frequency step word and then also the corresponding values for either the N divider numerator or the N divider denominator. All these calculations are explained in detail in the following application note:
In order to avoid all these complications, the best and easiest way to implement DCO mode is using Clock Builder Pro DCO mode tool. It will perform all the calculations and determine the required register values.
Many applications require output frequencies that are not integers and are represented using very specific decimal values. Clock generators and Jitter attenuators (Si534x/9x) devices are capable of generating all types of frequency outputs. When a required input-output configuration file is generated, Clock Builder Pro calculates the values of the M, N and P dividers according to the input-output frequencies.
The M and N dividers are in the form of a multiplication ratio. Calculating these values is very tricky when the output frequencies are not integers. In order to get the correct multiplication ratio, it is important to express the frequency values in an exact manner. This means that the decimal frequencies should not be rounded. They should be expressed in terms of fractions. Many times, the output frequency is in terms of repeating decimals. If these are rounded, then there is possibility of getting incorrect divider values.
For example, if a 33.3333… MHz output is required, it should be expressed as 100/3 MHz and not rounded to 33.333 MHz. The following table will show the difference in the M and N divider register values between 33.333 MHz and 100/3 MHz output frequency.
The left side shows register values when the output frequency is 33.333 MHz and the right side shows when it’s 100/3 MHz. As seen the M divider and N divider values are different and in order to get a perfect multiplication ratio, decimal frequencies should be expressed as fractions.
With limitation of Keysight E5052B, it can't measure phase noise when the carrier frequency less than 250MHz.
If one application need to see the phase noise at 100MHz while the carrier frequency is less than 250MHz, then they may need below two methods:
1. Test the frequency directly, and simply use the phase noise number at 40MHz or 20MHz, usually the far end to 100MHz phase noise trace is the extensions.
2. Double or quadruple the carrier frequency to make sure the carrier frequency larger than 250MHz and now you can the span of E5052B to 100MHz, and then plus 6 and 12 to get the actual carrier frequency phase noise. (Note: phase noise decreased by 6db every twice, it comes from a simplified function 20lg(f2/f1) ).
There is some tables to show the I2C data protocol in datasheet. Here is some figures to illustrate the protocol clearly.
1. Block Read
2. Block Write
3. Byte Read
Please be noted that Si53152/4/6/9 all need a valid input clock in order for the I2C interface to work.
CBPro implements the DCO function on a Si5395/94/92/45/44/42 by changing the numerator (Nx_NUM) as this gives a higher resolution than changing the N divider denominator (Nx_DEN). However the DCO function can be implemented by changing the Nx_DEN value and this KB article describes how to do this. Note that when changing the Nx_DEN value instead of the Nx_NUM value the minimum step size will increase by approximately the Nx divider value. This is because the Nx_NUM register is 44 bits and the Nx_DEN register is 32 bits. Changing the Nx_NUM term causes an extremely small non-linearity, which will not be a problem except for very rare applications. Changing the Nx_DEN term does not cause any non-linearity.
The DCO function of Si5395/94/92/45/44/42 devices is implemented by changing the Nx_DEN value in one of two ways:
Here is the procedure to implement a DCO function by changing the Nx_DEN term:
More information about DCO applications for Si5395/94/92/45/44/42 can be found at:
The Si5395/94/92/91/45/44/42/41 parts have a maximum output frequency of 1028 MHz. However, there are a few gaps below 1028 MHz which are not valid output frequencies. Why is this the case?
The output clock frequency is equal to the VCO frequency divided down by an output divider. Below 720 MHz, the output divider is able to operate in either fractional or integer mode. Therefore, any output frequency below 720 MHz can be synthesized. Above 720MHz, however, the output divider must be equal to an even integer value, with an exception made for the odd value of Fvco/Fout = 15. The dual constraints of an even integer divide ratio and a limited VCO tuning range lead to a couple of small gaps in the allowed output frequencies. More specifically, the frequencies from 720 MHz --> 733.334 MHz and 800 MHz --> 825 MHz are not valid output frequencies. The figure below shows a conceptual diagram of the valid and non-valid output frequency ranges. The blue areas show the valid output frequency ranges, and the red areas show the non-valid output frequency ranges.
The above definition of the valid and non-valid output frequency ranges holds true only if one unique frequency from the upper frequency range (720 MHz --> 1028 MHz) exists in the frequency plan. This is because selecting an output frequency from the 720 MHz --> 1028 MHz range fixes the VCO frequency. Therefore, selecting two or more unique output frequencies (noting that they both require integer dividers) from the upper range may present competing requirements for the VCO frequency and hence result in a non-synthesizable frequency plan.
A few examples of valid and non-valid frequency plans are listed below: